EZ80F917050SBCG Datasheet, PDF (14/30 Pages) Zilog, Inc. – Factory-default operating clock frequency at 50 MHz

Zdots^® SBC for eZ80AcclaimPlus!^™ Connectivity ASSP
Product Specification
10
Table 2. Zdots Input/Output Connector Pin Identification* (Continued)
Pin No Symbol
38
TDI/ZDA
39
GND
40
TRIGOUT
41
TCK/ZCL
Pull
Signal
Up/Down Direction
Input
Output
PU 10 kΩ Input
42
TMS
PU 10 kΩ Input
43
RTC_V_DD
44
EZ80CLK
Output
45
I²CSCL
PU 4 kΩ Bidirectional
46
GND
47
I²CSDA
PU 4 kΩ Bidirectional
48
GND
Power
49
FlashWE
PU 10 kΩ Input
50
GND
51
CS3
Output
52
DIS_IRDA PU 10 kΩ Input
53
RESET
PU 2 kΩ Bidirectional
54
WAIT
PU 2 kΩ Input
55
V_CC
56
GND
Comments
JTAG Data Input pin.
V_SS/Ground (0 V).
Active High trigger event indicator.
JTAG Input. High on reset enables ZDI mode;
Low on reset enables OCI debug.
JTAG Test Mode Select Input.
RTC supply. For proper operation of the Zdots,
this pin must be connected to the same power
source that powers the module (as it is done on
the Zilog^® development platform).
Synchronous CPU clock output.
I²C Bus Clock.
V_SS/Ground (0 V).
I²C Data Clock.
V_SS/Ground (0 V).
A Low enables a Write to external Flash memory
boot block area. If this pin is unconnected, the
Flash memory boot block area is Write-protected.
V_SS/Ground (0 V).
Used on the eZ80190, eZ80L92, eZ80F92,
eZ80F93 devices and connected to the CS8900
EMAC.
A Low disables the onboard IRDA transceiver to
use PC0/PC1 UART pins externally.
Reset Output from module or push-button reset.
Driving the WAIT pin Low forces the CPU to
provide additional clock cycles for an external
peripheral or external memory to complete its
Read or Write operation.
3.3 V supply input pin.
V_SS/Ground (0 V).
PS026102-1207
Pin Description