EZ80F917050SBCG Datasheet, PDF (15/30 Pages) Zilog, Inc. – Factory-default operating clock frequency at 50 MHz

Zdots^® SBC for eZ80AcclaimPlus!^™ Connectivity ASSP
Product Specification
11
Table 2. Zdots Input/Output Connector Pin Identification* (Continued)
Pin No Symbol
Pull
Signal
Up/Down Direction
Comments
57
HALT_SLP
Output, Active
Low
A Low on this pin indicates that the CPU enters
either HALT or SLEEP mode because of
execution of either a HALT or SLP instruction.
58
NMI
PU 10 kΩ Schmitt-trigger
Input, Active
Low
The NMI input is a higher priority input than the
maskable interrupts. It is always recognized at
the end of an instruction, regardless of the state
of the interrupt enable control bits. This input
includes a Schmitt-trigger to allow RC rise times.
This external NMI signal is combined with an
internal NMI signal generated from the WDT
block before being connected to the NMI input of
the CPU.
59
V_CC
60
Reserved
3.3 V supply input pin.
NC
Reserved—No Connection.
*Notes
1. External capacitive loads on RD, WR, IORQ, MREQ, D0–D7, and A0–A23 must be below 10 pF to satisfy
timing requirements for the CPU.
2. All unused inputs must be pulled to either V_DD or GND, depending on their inactive levels, to reduce power
consumption and to reduce noise sensitivity.
3. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
PS026102-1207
Pin Description