Z85C3008VSG Datasheet, PDF (71/81 Pages) Zilog, Inc. – CMOS SCC Serial Communications Controller

CMOS SCC Serial Communications Controller
Product Specification
63
Table 10 provides the Read/Write timing characteristics for the Z80C30 device.
Table 10. Z80C30 Read/Write Timing¹
8 MHz
10 MHz
No Symbol
1 TwAS
2 TdDS(AS)
3 TsCSO(AS)
4 ThCSO(AS)
5 TsCS1(DS)
6 ThCS1(DS)
7 TsiA(AS)
8 ThIA(AS)
9 TsRWR(DS)
10 ThRW(DS)
11 TsRWW(DS)
12 TdAS(DS)
13 TwDSI
14 TrC
15 TsA(AS)
16 ThA(AS)
17 TsDW(DS)
18 ThDW(DS)
19 TdDS(DA)
20 TdDSr(DR)
21 TdDSf(DR)
22 TdAS(DR)
Parameter
Min Max Min Max
AS Low Width
35
30
DS Rise to AS Fall Delay²
15
10
CS0 to AS Rise Setup Time²
0
0
CS0 to AS Rise Hold Time²
30
20
CS1 to DS Fall Setup Time²
65
50
CS1 to DS Rise Hold Time²
30
20
INTACK to AS Rise Setup Time
10
10
INTACK to AS Rise Hold Time
150
125
R/W (Read) to DS Fall Setup Time
65
50
R/W to DS Rise Hold Time
0
0
R/W (Write) to DS Fall Setup Time
0
0
AS Rise to DS Fall Delay
30
20
DS Low Width
Valid Access Recovery Time³
Address to AS Rise Setup Time²
Address to AS Rise Hold Time²
150
4TcPC
10
25
125
4TcPC
10
20
Write Data to DS Fall Setup Time
15
10
Write Data to DS Rise Hold Time
0
0
DS Fall to Data Active Delay
0
0
DS Rise to Read Data Not Valid Delay
0
0
DS Fall to Read Data Valid Delay
140
120
AS Rise to Read Data Valid Delay
250
190
Notes:
1. Units in nanoseconds (ns) unless otherwise noted.
2. Parameter does not apply to Interrupt Acknowledge transactions.
3. Parameter applies only between transactions involving the SCC.
4. Float delay is defined as the time required for a 0.5 V change in the output with a maximum DC load and a min-
imum AC load.
5. Open-drain output, measured with open-drain test load.
6. Parameter is system dependent. For any Z-SCC in the daisy chain. TdAS(DSA) must be greater than the sum of
TdAS(IEO) for the highest priority device in the daisy chain TsiEI(DSA) for the Z-SCC, and TdIElf(IEO) for each
device separating them in the daisy chain.
7. Parameter applies only to a Z-SCC pulling INT Low at the beginning of the Interrupt Acknowledge transaction.
8. Internal circuitry allows for the reset provided by the ZB to be recognized as a reset by the Z-SCC. All timing ref-
erences assume 20 V for a logic “1” and 08 V for a logic “0”.
PS011706-0511
Electrical Characteristics