Z85C3008VSG Datasheet, PDF (45/81 Pages) Zilog, Inc. – CMOS SCC Serial Communications Controller

CMOS SCC Serial Communications Controller
Product Specification
37
Read Registers
The SCC contains ten Read registers (eleven, counting the receive buffer (RR8) in each
channel). Four of these can be read to obtain status information (RR0, RR1, RR10, and
RR15). Two registers (RR12 and RR13) are read to learn the Baud Rate Generator time
constant. RR2 contains either the unmodified interrupt vector (Channel A) or the vector
modified by status information (Channel B). RR3 contains the Interrupt Pending (IP) bits
(Channel A only; see Figure 19). RR6 and RR7 contain the information in the SDLC
Frame Status FIFO, but is only read when WR15 D2 is set (see Figures 19 and 20 ).
Read Register 0
D7 D6 D5 D4 D3 D2 D1 D0
Read Register 3
D7 D6 D5 D4 D3 D2 D1 D0
Read Register 1
D7 D6 D5 D4 D3 D2 D1 D0
Rx Character Available
Zero Count
Tx Buffer Empty
DCD
Sync/Hunt
CTS
Tx Underrun/EOM
Break/Abort
All Sent
Residue Code 2
Residue Code 1
Residue Code 0
Parity Error
Rx Overrun Error
CRC/Framing Error
End of Frame (SDLC)
* Always 0 in B Channel
Read Register 10
D7 D6 D5 D4 D3 D2 D1 D0
Read Register 2
D7 D6 D5 D4 D3 D2 D1 D0
* Modified in B Channel
V0
V1
V2
V3
Interrupt
V4
Vector *
V5
V6
V7
Read Register 12
D7 D6 D5 D4 D3 D2 D1 D0
Figure 19. Read Register Bit Functions
Channel B Ext/Status IP
Channel B Tx IP
Channel B Rx IP
Channel A Ext/Status IP ^*
Channel A Tx IP
Channel A Rx IP
0
0
0
On Loop
0
0
Loop Sending
0
Two Clocks Missing
One Clocks Missing
TC0
TC1
TC2
TC3
TC4
TC5
TC6
TC7
Lower Byte
of Time Constant
PS011706-0511
Functional Descriptions