Z85C3008VSG Datasheet, PDF (35/81 Pages) Zilog, Inc. – CMOS SCC Serial Communications Controller

CMOS SCC Serial Communications Controller
Product Specification
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For FM encoding, the DPLL again counts from 0 to 31, but with a cycle corresponding to
two bit times. When the DPLL is locked, the clock edges in the data stream occur between
counts 15 and 16 and between counts 31 and 0. The DPLL looks for edges only during a
time centered on the 15 to 16 counting transition.
The 32x clock for the DPLL can be programmed to come from either the RTxC input or
the output of the BRG. The DPLL output can be programmed to be echoed out of the SCC
through the TRxC pin (if this pin is not being used as an input).
Data Encoding
The SCC can be programmed to encode and decode the serial data in four different meth-
ods; see Figure 12. In NRZ encoding, a 1 is represented by a High level and a 0 is repre-
sented by a Low level. In NRZI encoding, a 1 is represented by no change in level and a 0
is represented by a change in level.
In FM1 (more properly, bi-phase mark), a transition occurs at the beginning of every bit
cell. A 1 is represented by an additional transition at the center of the bit cell and a 0 is rep-
resented by no additional transition at the center of the bit cell.
In FM0 (bi-phase space), a transition occurs at the beginning of every bit cell. A 0 is repre-
sented by an additional transition at the center of the bit cell, and a 1 is represented by no
additional transition at the center of the bit cell.
In addition to these four methods, the SCC can be used to decode Manchester (bi-phase
level) data by using the DPLL in the FM mode and programming the receiver for NRZ
data. Manchester encoding always produces a transition at the center of the bit cell. If the
transition is 0 to 1, the bit is a 0. If the transition is 1 to 0, the bit is a 1.
PS011706-0511
Functional Descriptions