Z85C3008VSG Datasheet, PDF (40/81 Pages) Zilog, Inc. – CMOS SCC Serial Communications Controller

CMOS SCC Serial Communications Controller
Product Specification
32
The second write is the actual control word for the selected register, and if the second
operation is read, the selected Read register is accessed. All the SCC registers, including
the data registers, can be accessed in this fashion. The pointer bits are automatically
cleared after the Read or Write operation so that WR0 (or RR0) is addressed again.
Z80C30
All SCC registers are directly addressable. A command issued in WR0B controls how the
SCC decodes the address placed on the address/data bus at the beginning of a Read or
Write cycle. In the Shift Right mode, the channel select A/B is taken from AD0 and the
state of AD5 is ignored. In the Shift Left mode, the channel select A/B is taken from AD5
and the state of AD0 is ignored. AD7 and AD6 are always ignored as address bits and the
register address occupies AD4-AD1.
Z85C30/Z80C30 Setup
Initialization
The system program first issues a series of commands to initialize the basic mode of
operation. This is followed by other commands to qualify conditions within the selected
mode. For example, in the Asynchronous mode, character length, clock rate, number of
stop bits, and even or odd parity must be set first. The interrupt mode is set, and finally, the
receiver and transmitter are enabled.
Write Registers
The SCC contains 15 Write registers for the 80C30, while there are 16 for the 85C30 (one
more additional Write register if counting the transmit buffer) in each channel. These
Write registers are programmed separately to configure the functional ‘personality’ of the
channels. There are two registers (WR2 and WR9) shared by the two channels that are
accessed through either of them. WR2 contains the interrupt vector for both channels,
while WR9 contains the interrupt control bits and reset commands. Figures 15 through 18
display the format of each Write register.
PS011706-0511
Functional Descriptions