Z85C3008VSG Datasheet, PDF (65/81 Pages) Zilog, Inc. – CMOS SCC Serial Communications Controller

CMOS SCC Serial Communications Controller
Product Specification
57
Table 7. Z85C30 General Timing Table (continued)
8.5 MHz
10 MHz
16 MHz
No Symbol
19
TwTRXI
20
TcTRX
Parameter
TRxC Low Width⁶
TRxC Cycle Time^6,8
Min Max Min Max Min Max
150
120
80
488
400
244
21 TwEXT
DCD or CTS Pulse Width
200
120
70
22
TwSY
SYNC Pulse Width
200
120
70
Notes:
1. RxC is RTxC or TRxC, whichever is supplying the receive clock.
2. Synchronization of RxC to PCLK is eliminated in divide by four operation.
3. Parameter applies only to FM encoding/decoding.
4. TxC is TRxC or /RTxC, whichever is supplying the transmit clock.
5. External PCLK to RTxC or TxC synchronization requirement eliminated for PCLK divide-by-four operation.TRxC
and RTxC rise and fall times are identical to PCLK. Reference timing specs TfPC and TrPC.Tx and Rx input
clock slew rates should be kept to a maximum of 30 nsec. All parameters related to input CLK edges must be
referenced at the point at which the transition begins or ends, whichever is worst case.
6. Parameter applies only for transmitter and receiver; DPLL and Baud Rate Generator timing requirements are
identical to case PCLK requirements.
7. Enhanced Feature — RTxC used as input to internal DPLL only.
8. The maximum receive or transmit data rate is 1/4 PCLK.
9. Both RTxC and SYNC have 30 pF capacitors to ground connections.
PS011706-0511
Electrical Characteristics