Z85C3008VSG Datasheet, PDF (15/81 Pages) Zilog, Inc. – CMOS SCC Serial Communications Controller

CMOS SCC Serial Communications Controller
Product Specification
7
RxDA, RxDB
Receive Data (inputs, active High) . These signals receive serial data at standard TTL
levels.
RTxCA, RTxCB
Receive/Transmit Clocks (inputs, active Low) . These pins can be programmed in sev-
eral different operating modes. In each channel, RTxC can supply the receive clock, the
transmit clock, clock for the Baud Rate Generator, or the clock for the Digital Phase-
Locked Loop. These pins can also be programmed for use with the respective SYNC pins
as a crystal oscillator. The receive clock can be 1, 16, 32, or 64 times the data rate in Asyn-
chronous modes.
RTSA, RTSB
Request To Send (outputs, active Low) . When the Request To Send (RTS) bit in Write
Register 5 (see Figure 9 on page 22) is set, the RTS signal goes Low. When the RTS bit is
reset in the Asynchronous mode and Auto Enable is ON, the signal goes High after the
transmitter is empty. In Synchronous mode, it strictly follows the state of the RTS bit.
When Auto Enable is OFF, the RTS pins can be used as general-purpose outputs.
SYNCA, SYNCB
Synchronization (inputs or outputs, active Low) . These pins function as inputs, 
outputs, or part of the crystal oscillator circuit. In the Asynchronous Receive mode (crystal
oscillator option not selected), these pins are inputs similar to CTS and DCD. In this
mode, transitions on these lines affect the state of the Synchronous/Hunt status bits in
Read Register 0 (see Figure 8 on page 19) but have no other function.
In External Synchronization mode with the crystal oscillator not selected, these lines also
act as inputs. In this mode, SYNC must be driven Low for two receive clock cycles after
the last bit in the synchronous character is received. Character assembly begins on the 
rising edge of the receive clock immediately preceding the activation of SYNC.
In the Internal Synchronization mode (Monosync and Bisync) with the crystal oscillator
not selected, these pins act as outputs and are active only during the part of the receive
clock cycle in which synchronous characters are recognized. This synchronous condition
is not latched. These outputs are active each time a synchronization pattern is recognized
(regardless of character boundaries). In SDLC mode, these pins act as outputs and are
valid on receipt of a flag.
PS011706-0511
Pin Descriptions