Z85C3008VSG Datasheet, PDF (38/81 Pages) Zilog, Inc. – CMOS SCC Serial Communications Controller

CMOS SCC Serial Communications Controller
Product Specification
30
RR6 contain bits that are undefined. Bit D6 of RR7 (FIFO Data Available) determines if
status data is coming from the FIFO or directly from the status register, which sets to 1
when the FIFO is not empty. Not all status bits are stored in the FIFO. The All Sent, Parity,
and EOF bits bypass the FIFO. Status bits sent through the FIFO are Residue Bits (3),
Overrun, and CRC Error.
Frame Status FIFO Circuitry
RR1
SCC Status Reg
Residue Bits (3)
Overrun, CRC Error
Byte Counter
5 Bits
14 Bits
FIFO Array
10 Deep by 19 Bits Wide
Reset on Flag Detect
Increment on Byte Detection
Enable Count in SDLC
End of Frame Signal
Status Read Comp
Tail Pointer
4-Bit Counter
Head Pointer
4-Bit Counter
5 Bits
EOF = 1
6 Bits 8 Bits
4-Bit Comparator
Over
Equal
6-Bit MUX
EN
2 Bits
6 Bits
RR1
Bit 7 Bit 6 Bits 5-0
RR6
FIFO Enable
Interface
to SCC
RR7 D5-D0 + RR6 D7-D0
Byte Counter Contains 14 bits
for a 16 KByte maximum count
RR7 D6
FIFO Data available status bit Status Bit set to 1
When reading from FIFO
WR(15) Bit 2
Set Enables
Status FIFO
RR7 D7
FIFO Overflow Status Bit
MSB pf RR(7) is set on Status FIFO overflow
In SDLC Mode the following definitions apply
Figure 13. SDLC Frame Status FIFO
PS011706-0511
Functional Descriptions