Z85C3008VSG Datasheet, PDF (29/81 Pages) Zilog, Inc. – CMOS SCC Serial Communications Controller

CMOS SCC Serial Communications Controller
Product Specification
21
The Vector Includes Status (VIS) and No Vector (NV) bits in WR9 are ignored when bit
05 is set to 1.
When the INTACK and IEI pins are not being used, they should be pulled up to V_CC
through a resistor (10 K typical).
CPU/DMA Block Transfer
The SCC provides a Block Transfer mode to accommodate CPU block transfer functions
and DMA controllers. The Block Transfer mode uses the WAIT/REOUEST output in con-
junction with the Wait/Request bits in WR1. The WAIT/REOUEST output can be
defined under software control as a WAIT line in the CPU Block Transfer mode or as a
REQUEST line in the DMA Block Transfer mode.
To a DMA controller, the SCC REQUEST output indicates that the SCC is ready to trans-
fer data to or from memory To the CPU, the WAIT line indicates that the ESCC is not
ready to transfer data, thereby requesting that the CPU extend the I/O cycle. The DTR/
REQUEST line allows full-duplex operation under DMA control.
PS011706-0511
Functional Descriptions