Z5380 Datasheet, PDF(7/37 Page) Zilog, Inc. – SMALL COMPUTER SYSTEM INTERFACE (SCSI)

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Z5380 Datasheet, PDF (7/37 Pages) Zilog, Inc. – SMALL COMPUTER SYSTEM INTERFACE (SCSI)

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ZILOG

Z5380 SCSI

the SCSI Bus. The /RST signal will remain asserted until this

bit is reset or until an external /RESET occurs. After this bit

is set (1), IRQ goes active and all internal logic and control

registers are reset (except for the interrupt latch and the

Assert /RST bit). Writing a zero to bit 7 of the Initiator

Command Register deasserts the /RST signal. The status

of this bit is monitored by reading the Initiator Command

Mode Register. Address 2 (Read/Write). The Mode Reg-

ister controls the operation of the chip. This register deter-

mines whether the Z5380 operates as an Initiator or a

Target, whether DMA transfers are being used, whether

parity is checked, and whether interrupts are generated on

various external conditions. This register is read to check

the value of these internal control bits (Figure 8).

Address: 2

(Read/Write)

D7 D6 D5 D4 D3 D2 D1 D0

Arbitrate

DMA Mode

Monitor /BSY

Enable /EOP Interrupt

Enable Parity Interrupt

Enable Parity Checking

Target Mode

Block Mode DMA

Figure 8. Mode Register

Receive Register and set (0) for Start DMA Initiator Receive

mand Register, bit 0) must be True (1) for all DMA send

operations. In the DMA mode, /REQ and /ACK are auto-

matically controlled.

The DMA Mode bit is not reset upon the receipt of an /EOP

signal. Any DMA transfer is stopped by writing a zero into

this bit location; however, care must be taken not to cause

/CS and /DACK to be active simultaneously.

Bit 2. Monitor Busy. The Monitor Busy bit, when True (1),

causes an interrupt to be generated for an unexpected

loss of /BSY. When the interrupt is generated due to loss of

/BSY, the lower six bits of the Initiator Command Register

are reset (0) and all signals are removed from the SCSI

Bus.

Bit 3. Enable /EOP interrupt. The enable /EOP interrupt bit,

when set (1), causes an interrupt to occur when the /EOP

(End Of Process) signal is received from the DMA con-

troller logic.

Bit 4. Enable Parity Interrupt. The Enable Parity Interrupt

bit, when set (1), will cause an interrupt (IRQ) to occur if a

parity error is detected. A parity interrupt will only be

generated if the Enable Parity Checking bit (bit 5) is also

enabled (1).

Bit 5. Enable Parity Checking. The Enable Parity Checking

bit determines whether parity errors are ignored or saved

in the parity error latch. If this bit is reset (0), parity is

ignored. Conversely, if this bit is set (1), parity errors are

saved.

The following describes the operation of all bits in the

Initiator Command Register:

Bit 0. Arbitrate. The Arbitrate bit is set (1) to start the

Arbitration process. Prior to setting this bit, the Output Data

Only one data bit should be active for SCSI Bus Arbitration.

The Z5380 waits for a Bus-Free condition before entering

the Arbitration phase. The results of the Arbitration phase

is determined by reading the status bits LA and AIP

(Initiator Command Register, bits 5 and 6, respectively).

Bit 1. DMA Mode. The DMA Mode bit is normally used to

enable a DMA transfer and must be set (1) prior to writing

Start DMA Send Register, Start DMA Target Register, and

Start DMA Initiator Receiver Register. These three regis-

ters are used to start DMA transfers. The Target Mode bit

(Mode Register, bit 6) must be consistent with writes to

Start DMA Target Receive and Start DMA Initiator Receive

Registers; i.e., set (1) for a write to Start DMA Target

Bit 6. Target Mode. The Target Mode bit allows the Z5380

to operate as a SCSI Bus Initiator or Target. With this bit

reset (0), the Z5380 operates as a SCSI Bus Initiator.

Setting Target Mode bit to 1 programs the Z5380 to

operate as a SCSI Bus Target device. If the signals /ATN

and /ACK are to be asserted on the SCSI Bus, the Target

Mode bit must be reset (0). If the signals C//D, I//O, /MSG,

and /REQ are to be asserted on the SCSI Bus, the Target

Mode bit must be set (1).

Bit 7. Block Mode DMA. The Block Mode DMA bit controls

the characteristics of the DMA DRQ-/DACK handshake.

When this bit is reset (0) and the DMA Mode bit is active (1),

the DMA handshake uses the normal interlocked hand-

shake, and the rising edge of /DACK indicates the end of

each byte being transferred. In Block Mode operation,

when the Block Mode DMA bit is set (1) and DMA Mode bit

is active (1), the end of /IOR or /IOW signifies the end of

each byte transferred and /DACK is allowed to remain

active throughout the DMA operation. Ready can then be

used to request the next transfer.

PS97SCC0100

PS009101-0201

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