Z5380 Datasheet, PDF (15/37 Pages) Zilog, Inc. – SMALL COMPUTER SYSTEM INTERFACE (SCSI)

ZILOG
Z5380 SCSI
DRQ signal to generate /DACK and an /IOR or an /IOW
pulse to the Z5380. DRQ goes inactive when /DACK is
asserted and /DACK goes inactive some time after the
minimum read or write pulse width. This process is re-
peated for every byte. For this mode, /DACK should not be
allowed to cycle unless a transfer is taking place.
Block Mode DMA
Some popular DMA Controllers, such as the 9517A, pro-
vide a Block Mode DMA transfer. This type of transfer
allows the DMA controller to transfer blocks of data without
relinquishing the use of the Data Bus to the CPU after each
byte is transferred; thus, faster transfer rates are achieved
by eliminating the repetitive access and release of the CPU
Bus. If the Block Mode DMA bit (Mode Register, bit 7) is
active, the Z5380 begins the transfer by asserting DRQ.
The DMA controller then asserts /DACK for the remainder
of the block transfer. DRQ goes inactive for the duration of
the transfer. The Ready output is used to control the
transfer rate. Non-Block Mode DMA transfers end when
/DACK goes False, whereas Block Mode DMA transfers
end when /IOR or /IOW becomes inactive. Since this is the
case, DMA transfers may be started sooner in a Block
Mode transfer. To obtain optimum performance in Block
Mode operation, the DMA logic optionally uses the normal
DMA mode interlocking handshake. Ready is still available
to throttle the DMA transfer, but DRQ is 30 to 40 ns faster
than Ready and is used to start the cycle sooner. The
methods described under “Halting a DMA Operation”
apply for all DMA operations.
Pseudo DMA Mode
To avoid the tedium of monitoring and asserting the re-
quest/acknowledgment handshake signals for pro-
grammed I/O transfers, the system can be designed to
implement a pseudo DMA mode. This mode is imple-
mented by programming the Z5380 to operate in the DMA
mode, but using the CPU to emulate the DMA handshake.
DRQ may be detected by polling the DMA Request bit (bit
6) in the Bus and Status Register, by sampling the signal
through an external port, or by using it to generate a CPU
interrupt. Once DRQ is detected, the CPU can perform a
read or write data transfer. This CPU read/write is exter-
nally decoded to generate the appropriate /DACK and
/IOR or /IOW signals.
Often, external decoding logic is necessary to generate
the Z5380 /CS signal. This same logic may be used to
generate /DACK at no extra cost and provide an increased
performance in programmed I/O transfers.
Halting a DMA Operation
The /EOP signal is not the only way to halt a DMA transfer.
A bus phase mismatch or a reset of the DMA Mode bit
(Mode Register, bit 1) can also terminate a DMA cycle for
the current bus phase.
Using the /EOP Signal
If /EOP is used, it should be asserted for at least 100 ns
while /DACK and /IOR or /IOW are simultaneously active.
Note, however, that if /IOR or /IOW is not active, an interrupt
is generated, but the DMA activity continues. The /EOP
signal does not reset the DMA Mode bit. Since the /EOP
signal can occur during the last byte sent to the Output
Data Register, the /REQ and /ACK signals are monitored to
ensure that the last byte has transferred.
Bus Phase Mismatch Interrupt
A bus phase mismatch interrupt is used to halt the transfer
if operating as an Initiator. Using this method frees the host
from maintaining a data length counter and frees the DMA
logic from providing the /EOP signal. If performing an
Initiator send operation, the Z5380 requires /DACK to
cycle before /ACK goes inactive. Since phase changes
cannot occur if /ACK is active, either /DACK must be
cycled after the last byte is sent or the DMA Mode bit must
be reset in order to receive the phase mismatch interrupt.
Resetting the DMA Mode Bit
A DMA operation may be halted at any time simply by
resetting the DMA Mode bit. It is recommended that the
DMA Mode bit be reset after receiving an /EOP or bus
phase-mismatch interrupt. The DMA Mode bit must then
be set before writing any of the start DMA registers for
subsequent bus phases.
If resetting the DMA Mode bit is used instead of /EOP for
Target role operation, then care must be taken to reset this
bit at the proper time. If receiving data as a Target device,
the DMA Mode bit must be reset once the last DRQ is
received and before /DACK is asserted to prevent an
additional /REQ from occurring. Resetting this bit causes
DRQ to go inactive. However, the last byte received
remains in the Input Data Register and may be obtained
either by performing a normal CPU read or by cycling
/DACK and /IOR. In most cases, /EOP is easier to use when
operating as a Target device.
PS97SCC0100
PS009101-0201
15