Z5380 Datasheet, PDF (17/37 Pages) Zilog, Inc. – SMALL COMPUTER SYSTEM INTERFACE (SCSI)

ZILOG
Address: 6
(Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
/DB0
/DB1
/DB2
/DB3
/DB4
/DB5
/DB6
/DB7
Figure 32. Input Data Register
WRITE REGISTERS
Address: 0
(Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
/DB0
/DB1
/DB2
/DB3
/DB4
/DB5
/DB6
/DB7
Figure 34. Output Data Register
Address: 1
(Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Assert Data Bus
Assert /ATN
Assert /SEL
Assert /BSY
Assert /ACK
"0"
Test Mode
Assert /RST
Figure 35. Initiator Command Register
Address: 7
(Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
"X"
X = Don't Care
Z5380 SCSI
Figure 33. Reset Parity/Interrupt
Address: 2
(Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Arbitrate
DMA Mode
Monitor /BSY
Enable /EOP Interrupt
Enable Parity Interrupt
Enable Parity Checking
Target Mode
Block Mode DMA
Figure 36. Mode Register
Address: 3
(Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Assert I//O
Assert C//D
Assert /MSG
Assert /REQ
"X"
Figure 37. Target Command Register
PS97SCC0100
PS009101-0201
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