Z5380 Datasheet, PDF (10/37 Pages) Zilog, Inc. – SMALL COMPUTER SYSTEM INTERFACE (SCSI)

ZILOG
FUNCTIONAL DESCRIPTION (Continued)
DMA Registers
Three write-only registers are used to initiate all DMA
activity. They are: Start DMA Send, Start DMA Target
Receive, and Start DMA Initiator Receive. Performing a
write operation into one of these registers starts the de-
sired type of DMA transfer. Data presented to the Z5380 on
signals D7-D0 during the register write is meaningless and
has no effect on the operation. Prior to writing these
registers, the Block Mode DMA bit (bit 7), the DMA Mode
bit (bit 1), and the Target Mode bit (bit 6) in the Mode
Register must be appropriately set. The individual regis-
ters are briefly described as follows:
Start DMA Send. Address 5 (Write Only). This register is
written to initiate a DMA send, from the DMA to the SCSI
Bus, for either Initiator or Target role operations. The DMA
Mode bit (Mode Register, bit 1) is set prior to writing this
register.
Start DMA Target Receive. Address 6 (Write Only). This
register is written to initiate a DMA receive - from the SCSI
Bus to the DMA, for Target operation only. The DMA Mode
bit (bit 1) and the Target Mode bit (bit 6) in the Mode
Register must both be set (1) prior to writing this register.
Start DMA Initiator Receive. Address 7 (Write Only). This
register is written to initiate a DMA receive - from the SCSI
Bus to the DMA, for Initiator operation only. The DMA Mode
bit (bit 6) must be False (0) in the Mode Register prior to
writing this register.
Reset Parity/Interrupt. Address 7 (Read Only). Reading
this register resets the Parity Error bit (bit 5), the Interrupt
Request bit (bit 4), and the Busy Error bit (bit 2) in the Bus
and Status Register.
On-Chip SCSI Hardware Support
The Z5380 is easy to use because of its simple architec-
ture. The chip allows direct control and monitoring of the
SCSI Bus by providing a latch for each signal. However,
portions of the protocol define timings which are much too
quick for traditional microprocessors to control. Therefore,
hardware support has been provided for DMA transfers,
bus arbitration, phase change monitoring, bus disconnec-
tion, bus reset, parity generation, parity checking, and
device selection/reselection.
Arbitration is accomplished using a bus-free filter to con-
tinuously monitor /BSY. If /BSY remains inactive for at least
1.2 µs, the SCSI Bus is considered free and Arbitration may
begin. Arbitration will begin if the bus is free, /SEL is
inactive, and the Arbitrate bit (Mode Register, bit 0) is
Z5380 SCSI
active. Once arbitration has begun (/BSY asserted), an
arbitration delay of 2.2 µs must elapse before the Data Bus
can be examined to determine if Arbitration is enabled.
This delay is implemented in the controlling software
driver.
The Z5380 is a clockwise device. Delays such as bus-free
delay, bus-set delay, and bus-settle delay are imple-
mented using gate delays. These delays may differ be-
tween devices because of inherent process variations, but
are well within the proposed ANSI X3.131 - 1986 specifica-
tion.
Interrupts
The Z5380 provides an interrupt output (IRQ) to indicate a
task completion or an abnormal bus occurrence. The use
of interrupts is optional and may be disabled by resetting
the appropriate bits in the Mode Register or the Select
Enable Register.
When an interrupt occurs, the Bus and Status Register and
the Current SCSI Bus Status Register (Figures 12 and 10)
must be read to determine which condition created the
interrupt. IRQ can be reset simply by reading the Reset
Parity/Interrupt Register or by an external chip reset
/RESET active for 200 ns.
Assuming the Z5380 has been properly initialized, an
interrupt is generated if the chip is selected or reselected;
if an /EOP signal occurs during a DMA transfer; if a SCSI
Bus reset occurs; if a parity error occurs during a data
transfer; if a bus phase mismatch occurs; or if a SCSI Bus
disconnection occurs.
Selection/Reselection Interrupt
The Z5380 generates a select interrupt if /SEL is active (0),
its device ID is True and /BSY is False for at least a bus-
settle delay. If I//O is active, this is considered a reselect
interrupt. The correct ID bit is determined by a match in the
Select Enable Register. Only a single bit match is required
to generate an interrupt. This interrupt may be disabled by
writing zeros into all bits of the Select Enable Register.
If parity is supported, parity should be good during the
selection phase. Therefore, if the Enable Parity bit (Mode
Register, bit 5) is active, the Parity Error bit is checked to
ensure that a proper selection has occurred. The Enable
Parity Interrupt bit need not be set for this interrupt to be
generated.
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PS009101-0201
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