Z5380 Datasheet, PDF (35/37 Pages) Zilog, Inc. – SMALL COMPUTER SYSTEM INTERFACE (SCSI)

ZILOG
Z5380 NOTES
Z5380 SCSI
1. Edge-triggered /RST Interrupt. If the SCSI Bus is not
terminated, the /RST interrupt is continually gener-
ated.
6. Phase Mismatch Interrupt. A phase mismatch inter-
rupt is not guaranteed after a reselection for the
following reasons:
2. True End of DMA Interrupt. The Z5380 generates an
interrupt when it receives the last byte from the DMA,
not when the last byte is transferred to the SCSI Bus.
3. Return to Ready after /EOP Interrupt. When operat-
ing in Block Mode DMA, the Z5380 does not return the
Ready signal to a Ready condition. This locks up the
bus and prevents the CPU from executing.
– DMA Mode bit must be set in order to receive
a phase mismatch interrupt.
– DMA Mode bit can not be set unless /BSY is
active.
– /BSY can not be asserted until after the
reselection has occurred.
4. SCSI handshake after /EOP occurs. If an EOP oc-
curs when receiving data, a subsequent request will
cause /ACK to be asserted even though no DRQ is
issued.
5. Reselection Interrupt. During reselection, if the Tar-
get Command Register does not reflect the current
bus phase (most likely Data Out), the reselection
interrupt may get reset.
– Once /BSY is asserted, the Target may assert
/REQ in less than 500 ns.
– The phase mismatch interrupt is generated on
the active edge of /REQ. If the DMA Mode bit
is not set before the /REQ goes active, the
phase mismatch interrupt will not occur.
PS97SCC0100
PS009101-0201
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