Z5380 Datasheet, PDF (5/37 Pages) Zilog, Inc. – SMALL COMPUTER SYSTEM INTERFACE (SCSI)

ZILOG
Z5380 SCSI
Table 1. Register Summary
Address
A2 A1 A0 R/W
Register Name
000R
Current SCSI Data
0 0 0W
Output Data
0 0 1 R/W Initiator Command
0 1 0 R/W Mode
0 1 1 R/W Target Command
100R
Current SCSI Bus Status
1 0 0W
Select Enable
101R
Bus and Status
1 0 1W
110R
1 1 0W
111R
1 1 1W
Start DMA Send
Input Data
Start DMA Target Receive
Reset Parity/Interrupt
Start DMA Initiator Receive
Data Registers
Address: 0
(Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
/DB0
/DB1
/DB2
/DB3
/DB4
/DB5
/DB6
/DB7
Figure 4. Current SCSI Data Register
Address: 0
(Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
The data registers are used to transfer SCSI commands,
data, status, and message bytes between the micropro-
cessor Data Bus and the SCSI Bus. The Z5380 does not
interpret any information that passes through the data
registers. The data registers consist of the transparent
Current SCSI Data Register, the Output Data Register, and
the Input Data Register.
Current SCSI Data Register. Address 0 (Read Only). The
Current SCSI Data Register (Figure 4) is a read-only
register which allows the microprocessor to read the active
SCSI Data Bus. This is accomplished by activating /CS
with an address on A2-A0 of 000 and issuing an /IOR pulse.
If parity checking is enabled, the SCSI Bus parity is
checked at the beginning of the read cycle. This register
is used during a programmed I/O data read or during
Arbitration to check for higher priority arbitrating devices.
Parity is not guaranteed valid during Arbitration.
Output Data Register. Address 0 (Write Only). The Output
Data Register (Figure 5) is a write-only register that is used
to send data to the SCSI Bus. This is accomplished by
either using a normal CPU write, or under DMA control, by
using /IOW and /DACK. This register also asserts the
proper ID bits on the SCSI Bus during the Arbitration and
Selection phases.
/DB0
/DB1
/DB2
/DB3
/DB4
/DB5
/DB6
/DB7
Figure 5. Output Data Register
Initiator Command Register. Address 1 (Read/Write).
The Initiator Command Register (Figures 6 and 7) are read
and write registers which assert certain SCSI Bus signals,
monitors those signals, and monitors the progress of bus
arbitration. Many of these bits are significant only when
being used as an Initiator; however, most can be used
during Target role operation.
PS97SCC0100
PS009101-0201
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