Z5380 Datasheet, PDF (6/37 Pages) Zilog, Inc. – SMALL COMPUTER SYSTEM INTERFACE (SCSI)

ZILOG
Z5380 SCSI
FUNCTIONAL DESCRIPTION (Continued)
This bit should also be set during DMA send operations.
Address: 1
(Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Assert Data Bus
Assert /ATN
Assert /SEL
Assert /BSY
Assert /ACK
Lost Arbitration
Arbitration in Progress
Assert /RST
Bit 1. Assert /ATN. /ATN may be asserted on the SCSI Bus
by setting this bit to a one (1) if the Target Mode bit (Mode
Register, bit 6) is False. /ATN is normally asserted by the
initiator to request a Message Out bus phase. Note that
since Assert /SEL and Assert /ATN are in the same register,
a select with /ATN may be implemented with one CPU
write. /ATN may be deasserted by resetting this bit to zero.
A read of this register simply reflects the status of this bit.
Bit 2. Assert /SEL. Writing a one (1) into this bit position
asserts /SEL onto the SCSI Bus. /SEL is normally asserted
after Arbitration has been successfully completed. /SEL
may be disabled by resetting bit 2 to a zero. A read of this
register reflects the status of this bit.
Figure 6. Initiator Command Register
Address: 1
(Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Assert Data Bus
Assert /ATN
Assert /SEL
Assert /BSY
Assert /ACK
"0"
Test Mode
Assert /RST
Figure 7. Initiator Command Register
Bit 3. Assert /BSY. Writing a one (1) into this bit position
asserts /BSY onto the SCSI Bus. Conversely, a zero resets
the /BSY signal. Asserting /BSY indicates a successful
selection or reselection. Resetting this bit creates a Bus-
Disconnect condition. Reading this register reflects bit
status.
Bit 4. Assert /ACK. Bit 4 is used by the bus initiator to assert
/ACK on the SCSI Bus. In order to assert /ACK, the Target
Mode bit (Mode Register, bit 6) must be False. Writing a
zero to this bit deasserts /ACK. Reading this register
reflects bit status.
Bit 5. “0” (Write Bit). Bit 5 should be written with a zero for
proper operation.
Bit 5. LA (Lost Arbitration - Read Bit). Bit 5, when active,
indicates that the SCSI detected a Bus-Free condition,
arbitrated for use of the bus by asserting /BSY and its ID on
the Data Bus, and lost Arbitration due to /SEL being
asserted by another bus device. This bit is active only
when the Arbitrate bit (Mode Register, bit 0) is active.
The following describes the operation of all bits in the
Initiator Command Register:
Bit 0. Assert Data Bus. This bit, when set, allows the
contents of the Output Data Register to be enabled as chip
outputs on the signals /DB7-DB0. Parity is also generated
and asserted on /DBP.
When connected as an Initiator, the outputs are only
enabled if the Target Mode bit (Mode Register, bit 6) is 0,
the received signal I//O is False, and the phase signals (C/
/D, I//O, and /MSG) match the contents of the Assert C//D,
Assert I//O, and Assert /MSG in the Target Command
Register.
Bit 6. Test Mode (Write Bit). Bit 6 is written during a test
environment to disable all output drivers, effectively re-
moving the Z5380 from the circuit. Resetting this bit returns
the part to normal operation.
Bit 6. AIP (Arbitration in Process - Read Bit). Bit 6 is used
to determine if Arbitration is in progress. For this bit to be
active, the Arbitrate bit (Mode Register, bit 0) must have
been set previously. It indicates that a Bus-Free condition
has been detected and that the chip has asserted /BSY
and put the contents of the Output Data Register onto the
SCSI Bus. AIP will remain active until the Arbitrate bit is
reset.
Bit 7. Assert /RST. Whenever a one is written to bit 7 of the
Initiator Command Register, the /RST signal is asserted on
6
PS009101-0201
PS97SCC0100