Z5380 Datasheet, PDF (16/37 Pages) Zilog, Inc. – SMALL COMPUTER SYSTEM INTERFACE (SCSI)

ZILOG
READ REGISTERS
Address: 0
(Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
/DB0
/DB1
/DB2
/DB3
/DB4
/DB5
/DB6
/DB7
Figure 26. Current SCSI Data Register
Address: 1
(Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Assert Data Bus
Assert /ATN
Assert /SEL
Assert /BSY
Assert /ACK
Lost Arbitration
Arbitration in Progress
Assert /RST
Figure 27. Initiator Command Register
Address: 2
(Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Arbitrate
DMA Mode
Monitor /BSY
Enable /EOP Interrupt
Enable Parity Interrupt
Enable Parity Checking
Target Mode
Block Mode DMA
Figure 28. Mode Register
Z5380 SCSI
Address: 3
(Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Assert I//O
Assert C//D
Assert /MSG
Assert /REQ
"0"
Figure 29. Target Command Register
Address: 4
(Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
/DBP
/SEL
I//O
C//D
/MSG
/REQ
/BSY
/RST
Figure 30. Current SCSI Bus Status Register
Address: 5
(Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
/ACK
/ATN
Busy Error
Phase Match
Interrupt Request Active
Parity Error
DMA Request
End of DMA
Figure 31. Bus and Status Register
16
PS009101-0201
PS97SCC0100