Z86C72 Datasheet, PDF (67/71 Pages) Zilog, Inc. – IR MICROCONTROLLER

Zilog
Z8^® STANDARD CONTROL REGISTER DIAGRAMS
Z86C72/C92/L72/L92
IR Microcontroller
R247 P3M
D7 D6 D5 D4 D3 D2 D1 D0
R246 P2M
1
D7 D6 D5 D4 D3 D2 D1 D0
* Effects P34 and P35
0 Port 2 Open Drain*
1 Port 2 Push-pull
0 Digital Mode
1 Analog Mode
0 P32 = Input
P35 = Output
1 P32 = /DAV0/RDY0
P35 = RDY0//DAV0
00 P33 = Input
P34 = Output
01 P33 = Input
10 P34 = /DM
11
P33 = /DAV1/RDY1
P34 = RDY1//DAV1
0 P31 = Input (TIN)
P36 = Output (TOUT)
1 P31 = /DAV2/RDY2
P36 = RDY2//DAV2
Reserved (Must be 0)
Figure 52. Port 3 Mode Register
(F7H: Write Only)
R248 P01M
D7 D6 D5 D4 D3 D2 D1 D0
P00-P03 Mode
00 Output
01 Input*
1X A11-A8
Stack Selection
0 External
1 Internal*
P17-P10 Mode
00 Byte Output
01 Reserved
10 AD7-AD0
11 High-Impedance AD7AD0,
/AS, /DS, /R//W, A11-A8,
A15-A12, If Selected
External Memory Timing
0 Normal*
1 Extended
P07-P04 Mode
00 Output
01 Input*
1X A15-A12
* Default Setting After Reset.
Note: Only P00 and P07 are Available on Z86L71.
*Default Setting After Reset
P27-P20 I/O Definition
0 Defines Bit as OUTPUT
1 Defines Bit as INPUT*
Figure 54. Port 2 Mode Register
(F6H: Write Only)
R249 IPR
D7 D6 D5 D4 D3 D2 D1 D0
Interrupt Group Priority
000 Reserved
001 C>A>B
010 A>B>C
011 A>C>B
100 B>C>A
101 C>B>A
110 B>A>C
111 Reserved
IRQ1,IRQ4,Priority
(Group C)
0 IRQ1>IRQ4
1 IRQ4>IRQ1
IRQ0,IRQ2
Priority (Group B)
0 IRQ2>IRQ0
1 IRQ0>IRQ2
IRQ3,IRQ5Priority
(Group A)
0 IRQ5>IRQ3
1 IRQ3>IRQ5
Reserved (Must be 0)
Figure 55. Interrupt Priority Register
((0) F9H: Write Only)
Figure 53. Port 0 and 1 Mode Register
(F8H: Write Only)
DS97LVO0900
PRELIMINARY
6-67