Z86C72 Datasheet, PDF (22/71 Pages) Zilog, Inc. – IR MICROCONTROLLER

Z86C72/C92/L72/L92
IR Microcontroller
PIN FUNCTIONS
/DS (Output, active Low). Data Strobe is activated once for
each external memory transfer. For a READ operation,
data must be available prior to the trailing edge of /DS. For
WRITE operations, the falling edge of /DS indicates that
output data is valid.
/AS (Output, active Low). Address Strobe is pulsed once
at the beginning of each machine cycle. Address output is
through Port 0/Port 1 for all external programs. Memory
address transfers are valid at the trailing edge of /AS. Un-
der program control, /AS is placed in the high-impedance
state along with Ports 0 and 1, Data Strobe, and
Read/Write.
XTAL1 Crystal 1 (time-based input). This pin connects a
parallel-resonant crystal, ceramic resonator, LC, or RC
network or an external single-phase clock to the on-chip
oscillator input.
XTAL2 Crystal 2 (time-based output). This pin connects a
parallel-resonant, crystal, ceramic resonant, LC, or RC
network to the on-chip oscillator output.
R//W Read/Write (output, write Low). The R//W signal is
Low when the CCP is writing to the external program or
data memory.
R//RL (input). This pin, when connected to GND, disables
the internal ROM and forces the device to function as a
ROMless Z8. (Note that, when left unconnected or pulled
high to V_CC, the part functions normally as a Z8 ROM ver-
sion.)
Zilog
Port 0 (P07-P00). Port 0 is an 8-bit, bi-directional, CMOS
compatible port. These eight I/O lines are configured un-
der software control as a nibble I/O port, or as an address
port for interfacing external memory. The output drivers
are push-pull. Port 0 is placed under handshake control. In
this configuration, Port 3, lines P32 and P35 are used as
the handshake control /DAV0 and RDY0. Handshake sig-
nal direction is dictated by the I/O direction to Port 0 of the
upper nibble P07-P04. The lower nibble must have the
same direction as the upper nibble.
For external memory references, Port 0 can provide ad-
dress bits A11-A8 (lower nibble) or A15-A8 (lower and up-
per nibble) depending on the required address space. If
the address range requires 12 bits or less, the upper nibble
of Port 0 can be programmed independently as I/O while
the lower nibble is used for addressing. If one or both nib-
bles are needed for I/O operation, they must be configured
by writing to the Port 0 mode register. After a hardware re-
set, Port 0 is configured as an input port.
Port 0 is set in the high-impedance mode (if selected as an
address output) along with Port 1 and the control signals
/AS, /DS, and R//W through P3M bits D4 and D3(Figure
11).
A ROM mask option is available to program 0.4 V_DD
CMOS trip inputs on P00-P03 of the L72. This allows direct
interface to mouse/trackball IR sensors.
An optional 200 kOhm pull-up is available as a mask op-
tion on all Port 0 bits with nibble select. These pull-ups are
disabled when configured (bit by bit) as an output.
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PRELIMINARY
DS97LVO0900