Z86C72 Datasheet, PDF (37/71 Pages) Zilog, Inc. – IR MICROCONTROLLER

Zilog
Z86C72/C92/L72/L92
IR Microcontroller
CTR1 Register Description
In Demodulation Mode, this field defines the width of the
Mode. If it is 0, the Counter/Timers are in the transmit glitch that should be filtered out.
mode, otherwise they are in the demodulation mode.
1 ^{Initial_T8_Out/Rising_Edge. In Transmit Mode, if 0, the}
P36_Out/Demodulator_Input. In Transmit Mode, this bit output of T8 is set to 0 when it starts to count. If 1, the out-
defines whether P36 is used as a normal output pin or the put of T8 is set to 1 when it starts to count. When this bit is
combined output of T8 and T16.
set to 1 or 0, T8_OUT will be set to the opposite state of
this bit. This insures that when the clock is enabled a tran-
In Demodulation Mode, this bit defines whether the input _{sition occurs to the initial state set by CTR1, D1.}
signal to the Counter/Timers is from P20 or P31.
In Demodulation Mode, this bit is set to 1 when a rising
T8/T16_Logic/Edge _Detect. In Transmit Mode, this field _{edge is detected in the input signal. In order to reset it, a 1}
defines how the outputs of T8 and T16 are combined _{should be written to this location.}
(AND, OR, NOR, NAND).
Initial_T16 Out/Falling _Edge. In Transmit Mode, if it is 0,
In Demodulation Mode, this field defines which edge _{the output of T16 is set to 0 when it starts to count. If it is}
should be detected by the edge detector.
1, the output of T16 is set to 1 when it starts to count. This
Transmit_Submode/Glitch Filter. In Transmit Mode, this
field defines whether T8 and T16 are in the "Ping-Pong"
mode or in independent normal operation mode. Setting
this field to "Normal Operation Mode" terminates the "Ping-
Pong Mode" operation. When set to 10, T16 is immediately
bit is effective only in Normal or Ping-Pong Mode (CTR1,
D3, D2). When this bit is set, T16_OUT will be set to the
opposite state of this bit. This insures that when the clock
is enabled a transition occurs to the initial state set by
CTR1, D0.
forced to a 0. When set to 11, T16 is immediately forced to _{In Demodulation Mode, this bit is set to 1 when a falling}
a 1.
edge is detected in the input signal. In order to reset it, a 1
should be written to this location.
Note: Modifying CTR1, (D1 or D0) while the counters are
enabled will cause un-predictable output from T8/16_OUT.
DS97LVO0900
PRELIMINARY
6-37