Z86C72 Datasheet, PDF (51/71 Pages) Zilog, Inc. – IR MICROCONTROLLER

Zilog
Z86C72/C92/L72/L92
IR Microcontroller
Power-On Reset (POR). A timer circuit clocked by a ded- 1. Power Fail to Power OK status.
icated on-board RC oscillator is used for the Power-On Re-
set (POR) timer function. The POR time allows V_CC and ^{2. Stop-Mode Recovery (if D5 of SMR = 1).}
the oscillator circuit to stabilize before instruction execu-
1
tion begins.
3. WDT Time-Out.
The POR timer circuit is a one-shot timer triggered by one
of three conditions:
The POR time is a nominal 5 ms. Bit 5 of the Stop-Mode
Register determines whether the POR timer is bypassed
after Stop-Mode Recovery (typical for external clock, RC,
LC oscillators).
XTAL1
XTAL1
XTAL1
XTAL1
C1
C1
C1
C1
Rf
L
R
XTAL2
XTAL2
C2
C2
XTAL2
C2
Rd
XTAL2
Ceramic Resonator or Crystal
C1, C2 = 47 pF TYP *
f = 8 MHz
* Preliminary value including pin parasitics
LC
C1, C2 = 22 pF
L = 130 µH *
f = 3 MHz *
RC
@ 3V VCC (TYP)
C1 = 33 pF *
R = 1K *
32 kHz XTAL
C1 = 20 pF, C = 33 pF
Rd = 56 - 470K
Rf =10 M
Figure 36. Oscillator Configuration
XTAL1
XTAL2
External Clock
HALT. HALT turns off the internal CPU clock, but not the
XTAL oscillation. The counter/timers and external inter-
rupts IRQ0, IRQ1, IRQ2, IRQ3, and IRQ4 remain active.
The devices are recovered by interrupts, either externally
or internally generated. An interrupt request must be exe-
cuted (enabled) to exit HALT mode. After the interrupt ser-
vice routine, the program continues from the instruction af-
ter the HALT.
STOP. This instruction turns off the internal clock and ex-
ternal crystal oscillation and reduces the standby current
to 10 µA (typical) or less. STOP mode is terminated only
by a reset, such as WDT time-out, POR, SMR, or external
reset. This causes the processor to restart the application
program at address 000CH. In order to enter STOP (or
HALT) mode, it is necessary to first flush the instruction
pipeline to avoid suspending execution in mid-instruction.
To do this, the user must execute a NOP (opcode = FFH)
immediately before the appropriate sleep instruction, i.e.,
FF NOP ; clear the pipeline
6F STOP ; enter STOP mode
or
FF NOP ; clear the pipeline
7F HALT ; enter HALT mode
DS97LVO0900
PRELIMINARY
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