Z86C72 Datasheet, PDF (53/71 Pages) Zilog, Inc. – IR MICROCONTROLLER

Zilog
Z86C72/C92/L72/L92
IR Microcontroller
Comparator Output Port 3 (D0). Bit 0 controls the com- ware set on the condition of STOP recovery and reset by
parator used in Port 3. A 1 in this location brings the com- a power-on cycle. Bit 6 controls whether a low level or a
parator outputs to P34 and P37, and a 0 releases the Port
to its standard I/O configuration.
high level is required from the recovery source. Bit 5 con-
trols the reset delay after recovery. Bits D2, D3, and D4, of
1
the SMR register, specify the source of the Stop-Mode Re-
Stop-Mode Recovery Register (SMR). This register se- _{covery signal. Bit D0 determines if SCLK/TCLK are divided}
lects the clock divide value and determines the mode of _{by 16 or not. The SMR is located in Bank F of the Expand-}
Stop-Mode Recovery (Figure 38). All bits are write only ex- _{ed Register Group at address 0BH.}
cept bit 7, which is read only. Bit 7 is a flag bit that is hard-
SMR (0F) 0B
D7 D6 D5 D4 D3 D2 D1 D0
SCLK/TCLK Divide-by-16
0 OFF **
1 ON
Reserved (Must be 0)
Stop-Mode Recovery Source
000 POR Only *
001 Reserved
010 P31
0 11 P32
100 P33
101 P27
11 0 P2 NOR 0-3
111 P2 NOR 0-7
Stop Delay
0 OFF
1 ON *
Stop Recovery Level
0 Low *
1 High
Stop Flag
0 POR *
1 Stop Recovery**
* Default Setting After Reset
** Default Setting After Reset and Stop-Mode Recovery
Figure 38. Stop-Mode Recovery Register
DS97LVO0900
PRELIMINARY
6-53