Z86C72 Datasheet, PDF (55/71 Pages) Zilog, Inc. – IR MICROCONTROLLER

Zilog
Z86C72/C92/L72/L92
IR Microcontroller
SCLK/TCLK Divide-by-16 Select (D0). D0 of the SMR Stop-Mode Recovery Delay Select (D5). This bit, if Low,
controls a Divide-by-16 prescaler of SCLK/TCLK. The pur- disables the 5 ms /RESET delay after Stop-Mode Recov-
1 ^{pose of this control is to selectively reduce device power ery. The default configuration of this bit is one. If the "fast"}
consumption during normal processor execution (SCLK wake up is selected, the Stop-Mode Recovery source
control) and/or HALT mode (where TCLK sources interrupt needs to be kept active for at least 5TpC.
logic). After Stop-Mode Recovery, this bit is set to a 0.
Stop-Mode Recovery Edge Select (D6). A 1 in this bit po-
sition indicates that a High level on any one of the recovery
sources wakes the Z86L/CX2 from STOP mode. A 0 indi-
OSC
cates Low level recovery. The default is 0 on POR (Figure
36).
÷2
÷ 16
SCLK
SMR, D0 ^TCLK
Figure 40. SCLK Circuit
Stop-Mode Recovery Source (D2, D3, and D4). These
three bits of the SMR specify the wake up source of the
STOP recovery (Figure 39 and Table 5).
Table 5. Stop-Mode Recovery Source
D4 D3 D2
Description of Action
0 0 0 POR and/or external reset recovery
0 0 1 Reserved
0 1 0 P31 transition
0 1 1 P32 transition
1 0 0 P33 transition
1 0 1 P27 transition
1 1 0 Logical NOR of P20 through P23
1 1 1 Logical NOR of P20 through P27
Cold or Warm Start (D7). This bit is set by the device
upon entering STOP mode. It is a Read Only Flag bit. A 1
in D7 (warm) indicates that the device will awaken from a
SMR source or a WDT while in STOP mode. A 0 in this bit
(cold) indicates that the device will be reset by a POR,
WDT while not in STOP, or the device was awakened by a
low voltage standby mode.
Stop-Mode Recovery Register 2 (SMR). This register
determines the mode of the Stop Mode Recovery for
SMR2.
If SMR2 is used in conjunction with SMR, either of the
specified events will cause a Stop-Mode Recovery.
Note: Port pins configured as outputs are ignored as a
SMR or SMR2 recovery source. For example, if the NAND
of P23-20 is selected as the recovery source and P20 is
configured as an output then the remaining SMR pins
(P23-P21) form the NAND equation.
P33-P31 cannot wake up from stop mode if the input lines
are configured as analog input.
Note: Any Port 2 bit defined as an output will drive the cor-
responding input to the default state to allow the remaining
inputs to control the AND/OR function. Refer to SMR2 reg-
ister for other recover sources.
DS97LVO0900
PRELIMINARY
6-55