Z8673312PSG Datasheet, PDF (67/84 Pages) Zilog, Inc. – CMOS Z8 OTP Microcontrollers

CMOS Z8^® OTP Microcontrollers
Product Specification
63
Note:
WDT time-out in STOP Mode will not reset SMR,SMR2,PCON,
WDTMR, P2M, P3M, Ports 2 & 3 Data Registers, but will activate
the T_POR delay.
WDTMR Register Accessibility. The WDTMR register is accessible only during the first
60 internal system clock cycles from the execution of the first instruction after Power-On
Reset, Watchdog reset or a Stop Mode Recovery (Figure 33 and Figure 34). After this
point, the register cannot be modified by any means, intentional or otherwise. The
WDTMR cannot be read and is located in Bank F of the Expanded Register File at address
location 0Fh.
Clock Free WDT Reset. The WDT will enable the Z8 to reset the I/0 pins whenever the
WDT times out, even without a clock source running on the XTAL1 and XTAL2 pins.
WDTMR Bit D4 must be 0 for the clock Free WDT to work. The I/O pins will default to
their default settings.
WDTMR (F) 0F
D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP INT RC OSC External Clock
00
5 ms
128 TpC
01*
10 ms
256 TpC
10
25 ms
512 TpC
11
80 ms
2048 TpC
WDT During HALT
0 OFF
1 ON*
WDT During STOP
0 OFF
1 ON*
XTAL1/INT RC Select for WDT
0 On-Board RC*
1 XTAL
Reserved (Must be 0)
* Default setting after RESET
Figure 33. Watchdog Timer Mode Register Write Only
PS022901-0508
Electrical Characteristics