Z8673312PSG Datasheet, PDF (61/84 Pages) Zilog, Inc. – CMOS Z8 OTP Microcontrollers

CMOS Z8^® OTP Microcontrollers
Product Specification
57
FF NOP ; clear the pipeline
6F STOP ; enter STOP mode
or
FF NOP ; clear the pipeline
7F HALT ; enter HALT mode
STOP. This instruction turns off the internal clock and external crystal oscillation and
reduces the standby current to 10 microamperes or less. STOP Mode is terminated by one
of the following resets: either by WDT time-out, POR, a Stop Mode Recovery Source,
which is defined by the SMR register or external reset. This causes the processor to restart
the application program at address 000Ch.
Port Configuration Register (PCON). The PCON register configures the ports individu-
ally; comparator output on Port 3, open-drain on Port 0 and Port 1, low EMI on Ports 0, 1,
2 and 3, and low EMI oscillator. The PCON register is located in the expanded register file
at Bank F, location 00 (Figure 30).
PCON (FH) 00h
D7 D6 D5 D4 D3 D2 D1 D0
* Default Setting After Reset
Comparator Output Port 3
0 P34, P37 Standard Output*
1 P34, P37 Comparator Output*
0 Port 1 Open-Drain
1 Port 1 Push-pull Active*
0 Port 0 Open-Drain
1 Port 0 Push-pull Active*
0 Port 0 Low EMI
1 Port 0 Standard*
0 Port 1 Low EMI
1 Port 1 Standard*
0 Port 2 Low EMI
1 Port 2 Standard*
0 Port 3 Low EMI
1 Port 3 Standard*
Low EMI Character
0 Low EMI
1 Standard
Figure 30. Port Configuration Register (PCON) (Write Only)
PS022901-0508
Electrical Characteristics