Z8673312PSG Datasheet, PDF (42/84 Pages) Zilog, Inc. – CMOS Z8 OTP Microcontrollers

CMOS Z8^® OTP Microcontrollers
Product Specification
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CLR Clear (active High). This pin resets the internal address counter at the High Level.
CLK Address Clock. This pin is a clock input. The internal address counter increases by
one for each clock cycle.
Application Precaution
The production test-mode environment may be enabled accidentally during normal opera-
tion if excessive noise surges above V_CC occur on pins P31 and RESET.
In addition, processor operation of Z8 OTP devices may be affected by excessive noise
surges on the V_PP, EPM, OE pins while the microcontroller is in Standard Mode.
Recommendations for dampening voltage surges in both test and OTP mode include the
following:
• Using a clamping diode to V_CC
• Adding a capacitor to the affected pin
• Enable EPROM/Test Mode Disable OTP option bit.
Standard Mode
XTAL Crystal 1 (time-based input). This pin connects a parallel-resonant crystal, ceramic
resonator, LC, RC network, or external single-phase clock to the on-chip oscillator input.
XTAL2 Crystal 2 (time-based output). This pin connects a parallel-resonant crystal,
ceramic resonator, LC, or RC network to the on-chip oscillator output.
R/W Read/Write (output, write Low). The R/W signal is Low when the CCP is writing to
the external program or data memory (Z86E43/743/E44 only).
RESET Reset (input, active Low). Reset will initialize the MCU. Reset is accomplished
either through Power-On, Watchdog Timer reset, Stop Mode Recovery, or external reset.
During Power-On Reset and Watchdog Timer Reset, the internally generated reset drives
the reset pin low for the POR time. Any devices driving the reset line must be open-drain
in order to avoid damage from a possible conflict during reset conditions. Pull-up is pro-
vided internally. After the POR time, RESET is a Schmitt-triggered input. (RESET is
available on Z86E43/743/E44 only.)
To avoid asynchronous and noisy reset problems, the Z86E43/743/E44 is equipped with a
reset filter of four external clocks (4TpC). If the external reset signal is less than 4TpC in
duration, no reset occurs. On the fifth clock after the reset is detected, an internal RST sig-
nal is latched and held for an internal register count of 18 external clocks, or for the dura-
tion of the external reset, whichever is longer. During the reset cycle, DS is held active
Low while AS cycles at a rate of TpC/2. Program execution begins at location 000CH, 5-
10 TpC cycles after RESET is released. For Power-On Reset, the reset output time is 5 ms.
PS022901-0508
Electrical Characteristics