Z8673312PSG Datasheet, PDF (44/84 Pages) Zilog, Inc. – CMOS Z8 OTP Microcontrollers

CMOS Z8^® OTP Microcontrollers
Product Specification
40
4
MCU
4
Open-Drain
OEN
Port 0 (I/O)
Handshake Controls
DAV0 and RDY0
(P32 and P35)
PAD
Out
1.5
In
2.3 Hysteresis V_CC @ V_CC = 5.0V
R ~~ 500 KΩ
Auto Latch
Figure 18. Port 0 Configuration
Port 1 (P17-P10). Port 1 is an 8-bit, bidirectional, CMOS-compatible port with multi-
plexed Address (A7-A0) and Data (D7-D0) ports. These eight I/O lines can be pro-
grammed as inputs or outputs or can be configured under software control as an Address/
Data port for interfacing external memory. The input buffers are Schmitt-triggered and the
output buffers can be globally programmed as either push-pull or open-drain. Low EMI
output buffers can be globally programmed by the software. Port 1 can be placed under
handshake control. In this configuration, Port 3, lines P33 and P34 are used as the hand-
shake controls RDY1 and DAV1 (Ready and Data Available). To interface external mem-
ory, Port 1 must be programmed for the multiplexed Address/Data mode. If more than 256
external locations are required, Port 0 outputs the additional lines (see Figure 19).
PS022901-0508
Electrical Characteristics