Z8673312PSG Datasheet, PDF (60/84 Pages) Zilog, Inc. – CMOS Z8 OTP Microcontrollers

CMOS Z8^® OTP Microcontrollers
Product Specification
56
XTAL1
C1
XTAL1
C1
L
XTAL2
C2
Ceramic Resonator or Crystal
C1, C2 = 33 pF TYP *
f = 8 MHz
* Typical value including pin parasitics
C2
V_SS**
XTAL2
LC
C1, C2 = 22 pF
L = 130 μH *
f = 3 MHz
XTAL1
C1
R
XTAL2
RC
@ 5V V_CC (TYP)
C1 = 100 pF *
R = 2K *
f = 6 MHz *
XTAL1
XTAL2
External Clock
Figure 29. Oscillator Configuration
Power-On Reset (POR). A timer circuit clocked by a dedicated on-board RC oscillator is
used for the Power-On Reset (POR) timer function. The POR timer allows V_CC and the
oscillator circuit to stabilize before instruction execution begins.
The POR timer circuit is a one-shot timer triggered by one of three conditions:
1. Power fail to Power OK status
2. Stop Mode Recovery (if D5 of SMR=0)
3. WDT time-out
The POR time is a nominal 5 ms. Bit 5 of the STOP mode Register (SMR) determines
whether the POR timer is by-passed after Stop Mode Recovery (typical for an external
clock and RC/LC oscillators with fast start up times).
HALT. Turns off the internal CPU clock, but not the XTAL oscillation. The counter/timers
and external interrupt IRQ0, IRQ1, and IRQ2 remain active. The device is recovered by
interrupts, either externally or internally generated. An interrupt request must be executed
(enabled) to exit HALT Mode. After the interrupt service routine, the program continues
from the instruction after the HALT. In order to enter STOP or HALT Mode, it is neces-
sary to first flush the instruction pipeline to avoid suspending execution in mid-instruc-
tion. To do this, you must execute a NOP (Opcode = FFh) immediately before the
appropriate sleep instruction, that is:
PS022901-0508
Electrical Characteristics