Z8673312PSG Datasheet, PDF (43/84 Pages) Zilog, Inc. – CMOS Z8 OTP Microcontrollers

CMOS Z8^® OTP Microcontrollers
Product Specification
39
The Z86E43/743/E44 does not reset WDTMR, SMR, P2M, and P3M registers on a Stop-
Mode Recovery operation.
ROMless (input, active Low). This pin, when connected to GND, disables the internal
ROM and forces the device to function as a Z86C90/C89 ROMless Z8. (Note that, when
left unconnected or pulled High to V_CC, the device functions nor
Note: When using in ROM Mode in High EMI (noisy) environment, the
ROMless pins should be connected directly to V_CC.
DS (output, active Low). Data Strobe is activated once for each external memory transfer.
For a READ operation, data must be available prior to the trailing edge of DS. For WRITE
operations, the falling edge of DS indicates that output data is valid.
AS (output, active Low). Address Strobe is pulsed once at the beginning of each machine
cycle for external memory transfer. Address output is from Port 0/Port 1 for all external
programs. Memory address transfers are valid at the trailing edge of AS. Under program
control, AS is placed in the high-impedance state along with Ports 0 and 1, Data Strobe,
and Read/Write.
Port 0 (P07-P00). Port 0 is an 8-bit, bidirectional, CMOS-compatible I/0 port. These eight
I/O lines can be configured under software control as a nibble I/0 port, or as an address
port for interfacing external memory. The input buffers are Schmitt-triggered and nibble
programmed. Either nibble output that can be globally programmed as push-pull or open-
drain. Low EMI output buffers can be globally programmed by the software. Port 0 can be
placed under handshake control. In Handshake Mode, Port 3 lines P32 and P35 are used as
handshake control lines. The handshake direction is determined by the configuration
(input or output) assigned to Port 0’s upper nibble. The lower nibble must have the same
direction as the upper nibble.
For external memory references, Port 0 provides address bits A11-A8 (lower nibble) or Al
5-A8 (lower and upper nibble) depending on the required address space. If the address
range requires 12 bits or less, the upper nibble of Port 0 can be programmed independently
as I/O while the lower nibble is used for addressing. If one or both nibbles are needed for
I/O operation, they must be configured by writing to the Port 0 mode register. In ROMless
mode, after a hardware reset, Port 0 is configured as address lines Al 5-A8, and extended
timing is set to accommodate slow memory access. The initialization routine can include
re-configuration to eliminate this extended timing mode. In ROM mode, Port 0 is defined
as input after reset.
Port 0 can be set in the High-Impedance Mode if selected as an address output state, along
with Port 1 and the control signals AS, DS, and R/W (Figure 18).
PS022901-0508
Electrical Characteristics