Z86E30 Datasheet, PDF (57/66 Pages) Zilog, Inc. – Z8 4K OTP Microcontroller

Zilog
EXPANDED REGISTER FILE CONTROL REGISTERS
Z86E30/E31/E40
Z8 4K OTP Microcontroller
PCON (FH) 00H
D7 D6 D5 D4 D3 D2 D1 D0
* Default Setting After Reset
† Must Be 1 for Z86E30/E31
Comparator Output Port 3
0 P34, P37 Standard*
1 P34, P37 Comparator Output
0 Port 1 Open-Drain
1 Port 1 Push-Pull Active*†
0 Port 0 Open-Drain
1 Port 0 Push-pull Active*
0 Port 0 Low EMI
1 Port 0 Standard*
0 Port 1 Low EMI
1 Port 1 Standard*†
0 Port 2 Low EMI
1 Port 2 Standard*
0 Port 3 Low EMI
1 Port 3 Standard*
Low EMI Oscillator
0 Low EMI
1 Standard*
Figure 41. Port Configuration Register
Write Only
WDTMR (F) 0F
1
D7 D6 D5 D4 D3 D2 D1 D0
* Default setting after RESET
WDT TAP
00
01 _*
10
11
INT RC OSC
5 ms
10 ms
20 ms
80 ms
System Clock
128 SCLK
256 SCLK
512 SCLK
2048 SCLK
WDT During HALT
0 OFF
1 ON *
WDT During STOP
0 OFF
1 ON *
XTAL1/INT RC Select for WDT
0 On-Board RC _*
1 XTAL
Reserved (Must be 0)
Figure 43. Watch-Dog Timer Mode Register
Write Only
SMR2 (0F) DH
D7 D6 D5 D4 D3 D2 D1 D0
SMR (FH) 0B
D7 D6 D5 D4 D3 D2 D1 D0
SCLK/TCLK Divide-by-16
0 OFF **
1 ON
External Clock Divide by 2
0 SCLK/TCLK =XTAL/2*
1 SCLK/TCLK =XTAL
Stop Mode Recovery Source
000 POR Only and/or External Reset*
001 P30
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
Stop Delay
0 OFF
1 ON*
Stop Recovery Level
0 Low*
1 High
Stop Flag
0 POR*
1 Stop Recovery
* Default setting after RESET.
** Default setting after RESET and STOP-Mode Recovery.
Stop-Mode Recovery Source 2
00 POR only*
01 AND P20,P21,P22,P23
10 AND P20,P21,P22,P23,P24,
P25,P26,P27
Reserved (Must be 0)
Note: Not used in conjunction with SMR Source
Figure 44. STOP-Mode Recovery Register 2
Write Only
Figure 42. STOP-Mode Recovery Register
Write Only Except Bit D7, Which is Read Only
DS97Z8X0500
PRELIMINARY
57