Z86E30 Datasheet, PDF (39/66 Pages) Zilog, Inc. – Z8 4K OTP Microcontroller

Zilog
Z86E30/E31/E40
Z8 4K OTP Microcontroller
The counters can be programmed to start, stop, restart to internal microprocessor clock divided by four, or an exter-
continue, or restart from the initial value. The counters can nal signal input through Port 3. The Timer Mode register
1 ^{also be programmed to stop upon reaching zero (single configures the external timer input (P31) as an external}
pass mode) or to automatically reload the initial value and clock, a trigger input that can be retriggerable or non-retrig-
continue counting (modulo-n continuous mode).
gerable, or as a gate input for the internal clock. Port 3 line
P36 serves as a timer output (T_OUT) through which T0, T1
The counters, but not the prescalers, can be read at any _{or the internal clock can be output. The counter/timers can}
time without disturbing their value or count mode. The _{be cascaded by connecting the T0 output to the input of}
clock source for T1 is user-definable and can be either the _T1.
OSC
D1 (SMR)
÷2
D0 (SMR)
Internal Data Bus
Write
Write
Read
PRE0
Initial Value
Register
T0
Initial Value
Register
T0
Current Value
Register
6-Bit
8-bit
÷ 16
÷4
Down
Down
Counter
Counter
IRQ4
Internal
Clock
External Clock
Clock
Logic
÷4
6-Bit
Down
Counter
÷2
8-Bit
Down
Counter
TOUT
P36
IRQ5
Internal Clock
Gated Clock
Triggered Clock
TIN P31
PRE1
Initial Value
Register
T1
Initial Value
Register
T1
Current Value
Register
Write
Write
Read
Internal Data Bus
Figure 27. Counter/Timer Block Diagram
DS97Z8X0500
PRELIMINARY
39