Z86E30 Datasheet, PDF (27/66 Pages) Zilog, Inc. – Z8 4K OTP Microcontroller

Zilog
Z86E30/E31/E40
Z8 4K OTP Microcontroller
Port 1 (P17-P10). Port 1 is an 8-bit, bidirectional, CMOS- RDY1 and /DAV1 (Ready and Data Available). To inter-
compatible port with multiplexed Address (A7-A0) and face external memory, Port 1 must be programmed for the
1 ^{Data (D7-D0) ports. These eight I/O lines can be pro- multiplexed Address/Data mode. If more than 256 external}
grammed as inputs or outputs or can be configured under locations are required, Port 0 outputs the additional lines
software control as an Address/Data port for interfacing (Figure 19).
external memory. The input buffers are Schmitt-triggered
and the output buffers can be globally programmed as ei- ^{Port 1 can be placed in the high-impedance state along}
ther push-pull or open-drain. Low EMI output buffers can ^{with Port 0, /AS, /DS, and R//W, allowing the Z86E40 to}
be globally programmed by the software. Port 1 can be ^{share common resources in multiprocessor and DMA ap-}
placed under handshake control. In this configuration, Port ^plications.
3, lines P33 and P34 are used as the handshake controls
MCU
Port 2 (I/O)
Handshake Controls
/DAV1 and RDY1
(P33 and P34)
Open-Drain
OEN
PAD
Out
1.5
2.3V Hysteresis
In
R 500 kΩ
Auto Latch
Figure 19. Port 1 Configuration (Z86E40 Only)
DS97Z8X0500
PRELIMINARY
27