Z86E30 Datasheet, PDF (45/66 Pages) Zilog, Inc. – Z8 4K OTP Microcontroller

Zilog
Z86E30/E31/E40
Z8 4K OTP Microcontroller
SCLK/TCLK Divide-by-16 Select (D0). This bit of the PCON further helps lower EMI (i.e., D7 (PCON) = 0, D1
SMR controls a divide-by-16 prescaler of SCLK/TCLK. (SMR) = 1). The default setting is zero.
The purpose of this control is to selectively reduce device
power consumption during normal processor execution
STOP-Mode Recovery Source (D2, D3, and D4). These
1
(SCLK control) and/or HALT mode (where TCLK sources ^{three bits of the SMR register specify the wake up source}
counter/timers and interrupt logic).
of the STOP-Mode Recovery (Figure 32). Table 12 shows
the SMR source selected with the setting of D2 to D4. P33-
External Clock Divide-by-Two (D1). This bit can elimi- P31 cannot be used to wake up from STOP mode when
nate the oscillator divide-by-two circuitry. When this bit is programmed as analog inputs. When the STOP-Mode Re-
0, the System Clock (SCLK) and Timer Clock (TCLK) are covery sources are selected in this register then SMR2
equal to the external clock frequency divided by two. The register bits D0, D1 must be set to zero.
SCLK/TCLK is equal to the external clock frequency when
this bit is set (D1=1). Using this bit together with D7 of Note: If the Port2 pin is configured as an output, this output
level will be read by the SMR circuitry..
SMR2 D1 D0
00
VDD
P20
P23
SMR2 D1 D0
01
P20
P27
SMR2 D1 D0
10
SMR D4 D3 D2
000
VDD
P30
P31
P32
SMR
D4 D3 D2
00 1
01 0
01 1
SMR D4 D3 D2
10 0
SMR D4 D3 D2
10 1
P20
P33
P27
P23
Stop-Mode Recovery Edge
Select (SMR)
P33 From Pads
SMR D4 D3 D2
11 0
P20
P27
SMR D4 D3 D2
11 1
To POR
RESET
To P33 Data
Latch and IRQ1
MUX
Digital/Analog Mode
Select (P3M)
Figure 32. STOP-Mode Recovery Source
DS97Z8X0500
PRELIMINARY
45