Z86E30 Datasheet, PDF (18/66 Pages) Zilog, Inc. – Z8 4K OTP Microcontroller

Z86E30/E31/E40
Z8 4K OTP Microcontroller
No
Symbol
Parameter
Note [3]
V_CC
1 TdA(AS)
2 TdAS(A)
3 TdAS(DR)
4 TwAS
Address Valid to /AS Rise
Delay
/AS Rise to Address Float
Delay
/AS Rise to Read Data
Req’d Valid
/AS Low Width
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
5 TdAS(DS)
6 TwDSR
7 TwDSW
8 TdDSR(DR)
9 ThDR(DS)
Address Float to /DS Fall
/DS (Read) Low Width
/DS (Write) Low Width
/DS Fall to Read Data Req’d
Valid
Read Data to /DS Rise Hold
Time
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
10 TdDS(A)
11 TdDS(AS)
/DS Rise to Address Active
Delay
/DS Rise to /AS Fall Delay
12 TdR/W(AS)
13 TdDS(R/W)
R//W Valid to /AS Rise
Delay
/DS Rise to R//W Not Valid
14 TdDW(DSW)
15 TdDS(DW)
16 TdA(DR)
17 TdAS(DS)
Write Data Valid to /DS Fall
(Write) Delay
/DS Rise to Write Data Not
Valid Delay
Address Valid to Read Data
Req’d Valid
/AS Rise to /DS Fall Delay
18 TdDM(AS)
/DM Valid to /AS Fall Delay
20 ThDS(AS)
/DS Valid to Address Valid
Hold Time
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
Notes:
1. When using extended memory timing add 2 TpC
2. Timing numbers given are for minimum TpC
3. The V_CC voltage specification of 5.5V guarantees 5.0V +/- ±0.5V and
the V_CC voltage specification of 3.5V guarantees 3.5V only
Standard Test Load
All timing references use 0.7 V_CC for a logic 1 and 0.2 V_CC for a logic 0
For Standard Mode (not Low-EMI Mode for outputs) with SMR D1 = 0, D0 = 0
T_A = 0°C to 70°C
16 MHz
Min
Max
25
25
35
35
180
180
40
40
0
0
135
135
80
80
75
75
0
0
50
50
35
35
25
25
35
35
55
25
55
25
35
35
230
230
45
45
30
30
35
35
Zilog
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
2
2
1,2
2
1,2
1,2
1,2
2
2
2
2
2
2
2
1,2
2
2
18
PRELIMINARY
DS97Z8X0500