Z8E001 Datasheet, PDF (33/49 Pages) Zilog, Inc. – CMOS OTP Microcontroller

Zilog
READ/WRITE OPERATIONS
The control for each port is done on a bit-wise basis. All
bits are capable of operating as inputs or outputs, depend-
ing upon the setting of the port’s directional control regis-
ter. If configured as an input, each bit is given a Schmitt-
trigger. The output of the Schmitt-trigger is latched twice to
perform a synchronization function, and the output of the
synchronizer is fed to the port input register, which can be
read by software.
A write to a port input register has the effect of updating the
contents of the input register, but subsequent reads will not
necessarily return the same value that was written. If the
bit in question is defined as an input, the input register for
that bit position will contain the current synchronized input
value. Thus, writes to that bit position will be overwritten on
the next clock cycle with the newly sampled input data.
However, if the particular port bit is programmed as an out-
put, the input register for that bit will retain the software-up-
dated value since the port bits that are programmed as
outputs do not sample the value being driven out.
Any bit in either port can be defined as an output by setting
the appropriate bit in the directional control register. If this
is the case, the value held in the appropriate bit of the port
output register is driven directly onto the output pin. Note,
however, that this does not necessarily reflect the actual
output value. If an external error is holding an output pin
Z8E001
CMOS OTP Microcontroller
either high or low against the output driver, the software
read will return the DESIRED value, not the actual state
caused by the contention. When a bit is defined as an out-
put , the Schmitt-trigger on the input will be disabled to
save power.
Updates to the output register will take effect based upon
the timing of the internal instruction pipeline, but will be ref-
erenced to the rising edge of the clock. The output register
can be read at any time, and will return the current output
value that is held. No restrictions are placed on the timing
of reads and/or writes to any of the port registers with re-
spect to the others, but care should be taken when updat-
ing the directional control and special function registers.
When updating a directional control register, the special
function register should first be disabled. If this precaution
is not taken, spurious events could take place as a result
of the change in port I/O status. This is especially impor-
tant when defining changes in Port B, since the spurious
event referred to above could be one or more interrupts.
Clearing of the SFR register should be the first step in con-
figuring the port, and setting the SFR register should be
the last step in the port configuration process. To ensure
deterministic behavior, the SFR register should not be writ-
ten until the pins are being driven appropriately and all ini-
tialization has been completed.
PORT A
Port A is a general-purpose port. Figure 25 shows a block
diagram of Port A. Each of its lines can be independently
programmed as input or output via the Port A Directional
Control Register (PTADIR at 0D2H) as seen in Figure 24.
A bit set to a 1 in PTADIR configures the corresponding
bit in Port A as an output, while a bit cleared to 0 config-
ures the corresponding bit in Port A as an input.
The input buffers are Schmitt-triggered. Bits programmed
as outputs may be individually programmed as either
push-pull or open drain by setting the corresponding bit in
the Special Function Register (PTASFR, Figure 29.)
Register 0D2H
PTADIR Register
D7 D6 D5 D4 D3 D2 D1 D0
1 = Output
0 = Input
Figure 26. Port A Directional Control Register
DS97Z8X1300
PRELIMINARY
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