Z8E001 Datasheet, PDF (24/49 Pages) Zilog, Inc. – CMOS OTP Microcontroller

Z8E001
CMOS OTP Microcontroller
Indications of an Unreliable Design
There are two major indicators that are used in working de-
signs to determine their reliability over full lot and temper-
ature variations. They are:
Start-up Time. If start -up time is excessive, or varies wide-
ly from unit to unit, there is probably a gain problem. C1/C2
needs to be reduced; the amplifier gain is not adequate at
frequency, or crystal Rs is too large.
Output Level. The signal at the amplifier output should
swing from ground to V_CC. This indicates there is adequate
gain in the amplifier. As the oscillator starts up, the signal
amplitude grows until clipping occurs, at which point the
loop gain is effectively reduced to unity and constant oscil-
lation is achieved. A signal of less than 2.5 volts peak-to-
peak is an indication that low gain may be a problem. Ei-
ther C₁ or C₂ should be made smaller or a low-resistance
crystal should be used.
Zilog
Circuit Board Design Rules
The following circuit board design rules are suggested:
s To prevent induced noise the crystal and load capacitors
should be physically located as close to the Z8E001 as
possible.
s Signal lines should not run parallel to the clock oscillator
inputs. In particular, the crystal input circuitry and the
internal system clock output should be separated as
much as possible.
s V_CC power lines should be separated from the clock
oscillator input circuitry.
s Resistivity between XTAL1 or XTAL2 and the other pins
should be greater than 10 Mohms.
XTAL1 ¹⁷
C1
Z8E001
XTAL2 ¹⁶
C2
V_SS ¹⁵
Clock Generator Circuit
Signals A B
(Parallel Traces
Must Be Avoided)
XTAL1 ₁₇
Z8E001
Signal C
XTAL2 16
Z8E001
PB0
X1
X2
V_SS
V_CC
Board Design Example
(Top View)
Figure 16. Circuit Board Design Rules
24
PRELIMINARY
DS97Z8X1300