Z8E001 Datasheet, PDF (29/49 Pages) Zilog, Inc. – CMOS OTP Microcontroller

Zilog
Each 8-bit timer is given a pair of registers, which are both
readable and writable. One of the registers is defined to
contain the auto-initialization value for the timer, while the
second register contains the current value for the timer.
When a timer is enabled, the timer will decrement whatev-
er value is currently held in its count register, and will then
continue decrementing until it reaches 0, at which time an
interrupt will be generated and the contents of the auto-ini-
tialization register are optionally copied into the count val-
ue register. If auto-initialization is not enabled, the timer
will stop counting upon reaching 0 and control logic will
clear the appropriate control register bit to disable the tim-
er.This is referred to as "single-shot" operation. If auto-ini-
tialization is enabled, the timer will continue counting from
the initialization value. Software should not attempt to use
registers that are defined as having timer functionality.
Software is allowed to write to any register at any time, but
care should be taken if timer registers be updated while the
timer is enabled. If software updates the count value while
the timer is in operation, the timer will continue counting
based upon the software-updated value. This can produce
strange behavior if the software update occurred at exactly
the point that the timer was reaching 0 to trigger an inter-
rupt and/or reload.
Similarly, if software updates the initialization value regis-
ter while the timer is active, the next time that the timer
reaches 0, it will be initialized using the updated value.
Again, strange behavior could result if the initialization val-
ue register is being written while the timer is in the process
of being initialized. Whether initialization is done with the
new or old value is a function of the exact timing of the
write operation. In all cases, the Z8E001 will prioritize the
software write above that of a decrementer writeback.
However, when hardware clears a control register bit for a
timer that is configured for single-shot operation; the clear-
ing of the control bit will override a software write. Reading
either register can be done at any time, and will have no
effect on the functionality of the timer.
If a timer pair is defined to operate as a single 16-bit entity,
the entire 16-bit value must reach 0 before an interrupt is
generated. In this case, a single interrupt will be generat-
ed, and the interrupt will correspond to the even 8-bit timer.
For example, timers T2 and T3 are cascaded to form a sin-
gle 16-bit timer, so the interrupt for the combined timer will
be defined to be that of timer T2 rather than T3. When a
timer pair is specified to act as a single 16-bit timer, the
even timer registers in the pair (timer T0 or T2) will be de-
fined to hold the timer’s least significant byte; while the odd
timer in the pair will hold the timer’s most significant byte.
In parallel with the posting of the interrupt request, the in-
terrupting timer’s count value will be initialized by copying
the contents of the auto-initialization value register to the
count value register. It should be noted that any time that
a timer pair is defined to act as a single 16-bit timer, that
Z8E001
CMOS OTP Microcontroller
the auto-reload function will be performed automatically.
All 16-bit timers will continue counting while their interrupt
requests are active, and will operate in a free-running man-
ner.
If interrupts are disabled for a long period of time, it is pos-
sible for the timer to decrement to 0 again before its initial
interrupt has been responded to. This is a degenerate
case, and hardware is not required to detect this condition.
When the timer control register is written, all timers that are
enabled by the write will begin counting using the value
that is held in their count register. An auto-initialization is
not performed. All timers can receive an internal clock
source only. Each timer that is enabled will be updated ev-
ery 8th XTAL clock cycle.
If T0 and T1 are defined to work independently, then each
will work as an 8-bit timer with a single auto-initialization
register; T0ARLO for T0, and T1ARLO for T1. Each timer
will assert its predefined interrupt when it times out, and
will optionally perform the auto-initialization function. If T0
and T1 are cascaded to form a single 16-bit timer, then the
single 16-bit timer will be capable of performing as a Pulse-
Width Modulator (PWM). This timer is referred to as T01 to
distinguish it as having special functionality that is not
available when T0 and T1 act independently.
When T01 is enabled, it can use a pair of 16-bit auto-initial-
ization registers. In this mode, one 16-bit auto-initialization
value is composed of the concatenation of T1ARLO and
T0ARLO, and the second auto-initialization value is com-
posed of the concatenation of T1ARHI and T0ARHI. When
T01 times out, it will alternately initialize its count value us-
ing the LO auto-init pair followed by the HI auto-init pair.
This functionality corresponds to a PWM where the T1 in-
terrupt will define the end of the HI section of the wave-
form, and the T0 interrupt will mark the end of the LO por-
tion of the PWM waveform.
To use the cascaded timers as a PWM, one must initialize
the T0 and T1 count registers to work in conjunction with
the port pin. The user should initialize the T0 and T1 count
registers to the PWM_HI auto-init value to obtain the de-
sired PWM behavior. The PWM is arbitrarily defined to use
the LO autoreload registers first. This implies that it had
just timed out after beginning in the HI portion of the PWM
waveform. As such, the PWM is defined to assert the T1
interrupt after the first timeout interval.
After the auto-initialization has been completed, decre-
menting occurs for the number of counts defined by the
PWM_LO registers. When decrementing again reaches 0,
the T0 interrupt is asserted; and auto-init using the
PWM_HI registers occurs. Decrementing occurs for the
number of counts defined by the PWM_HI registers until
reaching 0, at which time the the T1 interrupt is asserted,
and the cycle begins again.
DS97Z8X1300
PRELIMINARY
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