Z8E001 Datasheet, PDF (17/49 Pages) Zilog, Inc. – CMOS OTP Microcontroller

Zilog
Z8E001
CMOS OTP Microcontroller
Table 5. Control and Peripheral Register Reset Values
Register
(HEX)
FF
FE
FD
FC
FB
FA
F9-F0
EF-E0
DF-D8
D7
D6
D5
D4
D3
D2
D1
D0
CF
CE
CD
CC
CB
CA
C9
C8
C7
C6
C5
C4
C3
C2
C1
C0
Register
Name
Bits
7 6 5 4 3 2 1 0 Comments
Stack Pointer
0 0 U U U U U U Stack pointer is not affected by RESET
Reserved
Register Pointer U U U U 0 0 0 0 Register pointer is not affected by RESET
Flags
U U U U U U * * Only WDT & SMR flags are affected by RESET
Interrupt Mask
0 0 0 0 0 0 0 0 All interrupts masked by RESET
Interrupt Request 0 0 0 0 0 0 0 0 All interrupt requests cleared by RESET
Reserved
Virtual Copy
Virtual Copy of the Current Working Register Set
Reserved
PortB Spec. Func. 0 0 0 0 0 0 0 0 Deactivates all port special functions after RESET
PortB Control
0 0 0 0 0 0 0 0 Defines all bits as inputs in PortB after RESET
PortB Output
U U U U U U U U Output register not affected by RESET
PortB Input
U U U U U U U U Current sample of the input pin following RESET
PortA Spec. Func. 0 0 0 0 0 0 0 0 Deactivates all port special functions after RESET
PortA Control
0 0 0 0 0 0 0 0 Defines all bits as inputs in PortA after RESET
PortA Output
U U U U U U U U Output register not affected by RESET
PortA Input
U U U U U U U U Current sample of the input pin following RESET
Reserved
Reserved
T1VAL
U U U U U UUU
T0VAL
U U U U U UUU
T3VAL
U U U U U UUU
T2VAL
U U U U U UUU
T3AR
U U U U U UUU
T2AR
U U U U U UUU
T1ARHI
U U U U U UUU
T0ARHI
U U U U U UUU
T1ARLO
U U U U U UUU
T0ARLO
U U U U U UUU
WDTHI
1 1 1 1 1111
WDTLO
1 1 1 1 1111
TCTLHI
1 1 1 1 1 0 0 0 WDT Enabled in HALT Mode, WDT timeout at
maximum value, STOP Mode disabled
TCTLLO
0 0 0 0 0 0 0 0 All standard timers are disabled
* The SMR and WDT flags are set indicating the source of
the RESET.
D1
D0
0
0
0
1
1
0
1
1
Reset Source
/RESET Pin
SMR Recovery
WDT Reset
Reserved
DS97Z8X1300
PRELIMINARY
17