Z8E001 Datasheet, PDF (16/49 Pages) Zilog, Inc. – CMOS OTP Microcontroller

Z8E001
CMOS OTP Microcontroller
Z8^PLUS CORE
The Z8E001 is based on the Zilog Z8^Plus Core Architec-
ture. This core is capable of addressing up to 64KBytes of
program memory and 4KBytes of RAM. Register RAM is
accessed as either 8 or 16 bit registers using a combina-
tion of 4, 8, and 12 bit addressing modes. The architecture
Zilog
supports up to 15 vectored interrupts from external and in-
ternal sources. The processor decodes 44 CISC instruc-
tions using six addressing modes. See the Z8^Plus User’s
Manual (UM97Z8X0300) for more information.
RESET
This section describes the Z8E001 reset conditions, reset
timing, and register initialization procedures. Reset is gen-
erated by the Reset Pin, Watch-Dog Timer (WDT), and
Stop-Mode Recovery (SMR).
A system reset overrides all other operating conditions and
puts the Z8E001 into a known state. To initialize the chip’s
internal logic, the /RESET input must be held Low for at
least 30 XTAL clock cycles. The control registers and ports
are reset to their default conditions after a reset from the
/RESET pin. The control registers and ports are not reset
to their default conditions after wakeup from Stop Mode or
WDT timeout.
During RESET, the program counter is loaded with 0020H.
I/O ports and control registers are configured to their de-
fault reset state. Resetting the Z8E001 does not effect the
contents of the general-purpose registers.
RESET PIN OPERATION
The Z8E001 hardware /RESET pin initializes the control
and peripheral registers, as shown in Table 4. Specific re-
set values are shown by 1 or 0, while bits whose states are
unchanged are indicated by the letter U.
/RESET must be held low until the oscillator stabilizes,
then for an additional 30 XTAL clock cycles to be sure that
the internal reset is complete. The /RESET pin has a
Schmitt-Trigger input with a trip point. There is no high side
protection diode. The user should place an external diode
from /RESET to V_CC. A pull-up resistor on the /RESET pin
is approximately 500 K-ohms, typical.
Program execution starts 10 XTAL clock cycles after /RE-
SET has returned High. The initial instruction fetch is from
location 0020H. Figure 7 shows reset timing.
After a reset, the first routine executed must be one that
initializes the TCTLHI control register to the required sys-
tem configuration, followed by initialization of the remain-
ing control registers.
16
PRELIMINARY
DS97Z8X1300