Z8E001 Datasheet, PDF (21/49 Pages) Zilog, Inc. – CMOS OTP Microcontroller

Zilog
The TCTLHI bits for control of the WDT are described be-
low:
WDT Time Select (D6, D5, D4). Bits 6, 5, and 4 determine
the time-out period. Figure 11 shows the range of timeout
values that can be obtained. The default values of D6, D5,
and D4 are all 1, thus setting the WDT to its maximum tim-
eout period when coming out of RESET.
Figure 13. Time-Out Period of the WDT
D6 D5 D4
Crystal
Clocks to
Timeout
Time-Out
Using a
10 MHZ Crystal
0 0 0 Disabled
Disabled
0 0 1 65,536 TpC
6.55 ms
0 1 0 131,072 TpC
13.11 ms
0 1 1 262,144 TpC
26.21 ms
1 0 0 524,288 TpC
52.43 ms
1 0 1 1,048,576 TpC 104.86 ms
1 1 0 2,097,152 TpC 209.72 ms
1 1 1 4,194,304 TpC 419.43 ms
Notes:
TpC = XTAL clock cycle
The default on reset is D6 = D5 = D4 = 1.
Z8E001
CMOS OTP Microcontroller
WDT During HALT (D7). This bit determines whether or
not the WDT is active during HALT Mode. A 1 indicates ac-
tive during HALT. A 0 prevents the WDT from resetting the
part while halted.Coming out of reset, the WDT will be en-
abled during HALT Mode.
STOP MODE (D3). Coming out of RESET, the Z8E001 will
have STOP Mode disabled. If an application desires to use
STOP Mode, bit D3 must be cleared immediately upon
leaving RESET. If bit D3 is set, the STOP instruction will
execute as a NOP. If bit D3 is cleared, the STOP instruc-
tion will enter Stop Mode. Whenever the Z8E001 wakes up
after having been in STOP Mode, the STOP Mode will,
once again, be disabled.
Bits 2, 1 and 0. These bits are reserved and must be 0.
POWER-DOWN MODES
In addition to the standard RUN mode, the Z8E001 MCU
supports two Power-Down modes to minimize device cur-
rent consumption. The two modes supported are HALT
and STOP.
HALT MODE OPERATION
The HALT Mode suspends instruction execution and turns
off the internal CPU clock. The on-chip oscillator circuit re-
mains active so the internal clock continues to run and is
applied to the timers and interrupt logic.
To enter the HALT Mode, the Z8E001 only needs to exe-
cute a HALT instruction. It is NOT necessary to execute a
NOP instruction immediately before the HALT instruction.
The HALT Mode may be exited by servicing an interrupt,
either externally or internally generated. Upon completion
of the interrupt service routine, the user program continues
from the instruction after the HALT instruction.
The HALT Mode may also be exited via a /RESET activa-
tion or a Watch-Dog Timer (WDT) timeout. In these cases,
program execution will restart at the reset restart address
0020H.
7F HALT ;enter HALT Mode
DS97Z8X1300
PRELIMINARY
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