Z8E001 Datasheet, PDF (20/49 Pages) Zilog, Inc. – CMOS OTP Microcontroller

Z8E001
CMOS OTP Microcontroller
Zilog
Z8E001 WATCH-DOG TIMER (WDT)
The WDT is a retriggerable one-shot 16-bit timer that re-
sets the Z8E001 if it reaches its terminal count. The WDT
is driven by the XTAL2 clock pin. In order to provide the
longer timeout periods desired in applications, the watch-
dog timer is only updated every 64th clock cycle. When op-
erating in the RUN or HALT Modes, a WDT timeout reset
is functionally equivalent to an interrupt vectoring the PC
to 0020H and setting the WDT flag to a one state. Coming
out of RESET, the WDT will be fully enabled with its time-
out value set at the maximum value, unless otherwise pro-
grammed during the first instruction. Subsequent execu-
tions of the WDT instruction reinitialize the watchdog timer
registers, C2H and C3H, to their initial values as defined by
bits D6, D5, and D4 of the TCTLHI register. The WDT can-
not be disabled except on the first cycle after RESET, and
if the device enters Stop mode.
The WDT instruction should be executed often enough to
provide some margin before allowing the WDT registers to
get near 0. Because the WDT timeout periods are relative-
ly long, a WDT reset will occur in the unlikely event that
the WDT times out on exactly the same cycle that the WDT
instruction is executed.
The WDT and SMR flags are the only flags that are affect-
ed by the external RESET pin. /RESET clears both the
WDT and SMR flags. A WDT timeout sets the WDT flag.
The STOP instruction sets the SMR flag. This behavior en-
ables software to determine whether a pin RESET oc-
curred, or whether a WDT timeout occurred, or whether a
return from STOP Mode occurred. Reading the WDT flag
does not reset it to zero, the user must clear it via software.
Failure to clear the flag may result in undefined behavior.
0C1
TCTLHI
D7
D6 D5 D4
D3 D2
D1 D0
* Designates Default Value after RESET
RESERVED (MUST BE 0)
0 = STOP MODE ENABLED
1 = STOP MODE DISABLED*
D6 D5 D4 WDT TIMEOUT VALUE
---- --- ---- --------------------------------
0 0 0 DISABLED
0 01
65,536 TpC
0 10
131,072 TpC
0 11
262,144 TpC
1 00
524,288 TpC
1 0 1 1,048,576 TpC
1 10
2,097,152 TpC
1 11
4,194,304 TpC*
(XTAL CLOCKS TO TIMEOUT)
1 = WDT ENABLED IN HALT MODE*
0 = WDT DISABLED IN HALT MODE
Figure 12. Z8E001 TCTLHI Register for Control of WDT
Note: The WDT can only be disabled via software if the
first instruction out of RESET performs this function. Logic
within the Z8E001 will detect that it is in the process of
executing the first instruction after the part leaves RESET.
During the execution of this instruction, the upper five bits
of the TCTLHI register can be written. After this first
instruction, hardware will not allow the upper five bits of
this register to be written.
20
PRELIMINARY
DS97Z8X1300