Z8PE003 Datasheet, PDF (31/48 Pages) Zilog, Inc. – FEATURE-ENHANCED Z8PLUS 1K ROM ONE-TIME PROGRAMMABLE (OTP) MICROCONTROLLER

ZiLOG
Z8PE003
Z8Plus OTP Microcontroller
If a timer pair is defined to operate as a single 16-bit entity,
the entire 16-bit value must reach 0 before an interrupt is
generated. In this case, a single interrupt is generated, and
the interrupt corresponds to the even 8-bit timer.
Example: Timers T2 and T3 are cascaded to form a single 16-
bit timer. The interrupt for the combined timer is
defined to be generated by timer T2 rather than T3.
When a timer pair is specified to act as a single 16-
bit timer, the even timer registers in the pair (timer
T0 or T2) is defined to hold the timer’s least
significant byte. In contrast, the odd timer in the pair
holds the timer’s most significant byte.
In parallel with the posting of the interrupt request, the in-
terrupting timer’s count value is initialized by copying the
contents of the auto-initialization value register to the count
value register.
Note: Any time that a timer pair is defined to act as a single 16-
bit timer, the auto-reload function is performed automat-
ically.
All 16-bit timers continue counting while their interrupt re-
quests are active and operate independently of each other.
If interrupts are disabled for a long period of time, it is pos-
sible for the timer to decrement to 0 again before its initial
interrupt is responded to. This condition is termed a degen-
erate case, and hardware is not required to detect it.
When the timer control register is written, all timers that are
enabled by the WRITE begin counting from the value in the
count register. In this case, an auto-initialization is not per-
formed. All timers can receive an internal clock source input
only. Each enabled timer is updated every 8th XTAL clock
cycle.
If T0 and T1 are defined to work independently, then each
works as an 8-bit timer with a single auto-initialization reg-
ister (T0ARLO for T0, and T1ARLO for T1). Each timer as-
serts its predefined interrupt when it times out, optionally
performing the auto-initialization function. If T0 and T1 are
cascaded to form a single 16-bit timer, then the single 16-
bit timer is capable of performing as a Pulse-Width Mod-
ulator (PWM). This timer is referred to as T01 to distinguish
it as having special functionality that is not available when
T0 and T1 act independently.
When T01 is enabled, it can use a pair of 16-bit auto-ini-
tialization registers. In this mode, one 16-bit auto-initial-
ization value is composed of the concatenation of T1ARLO
and T0ARLO. The second auto-initialization value is com-
posed of the concatenation of T1ARHI and T0ARHI. When
T01 times out, it alternately initializes its count value using
the Low auto-init pair, followed by the High auto-init pair.
This functionality corresponds to a PWM. That is, the T1
interrupt defines the end of the High section of the wave-
form, and the T0 interrupt marks the end of the Low portion
of the PWM waveform.
The PWM begins counting with whatever data is held in the
count registers. After this value expires, the first reload de-
pends on the state of the PB1 pin if T_OUT mode is selected.
Otherwise, the Low value is applied first.
After the auto-initialization is completed, decrementing oc-
curs for the number of counts defined by the PWM_LO reg-
isters. When decrementing again reaches 0, the T0 interrupt
is asserted; and auto-init using the PWM_HI registers oc-
curs. Decrementing occurs for the number of counts defined
by the PWM_HI registers until reaching 0. From there, the
T1 interrupt IRQ2 is asserted, and the cycle begins again.
The internal timers can be used to trigger external events
by toggling the PB1 output when generating an interrupt.
This functionality can only be achieved in conjunction with
the port unit defining the appropriate pin as an output signal
with the timer output special function enabled. In this mode,
the port output is toggled when the timer count reaches 0,
and continues toggling each time that the timer times out.
T_OUT Mode
The PortB special function register PTBSFR (0D7H; Figure
23) is used in conjunction with the Port B directional control
register PTBDIR (0D6; Figure 24) to configure PB1 for T_OUT
operation for T0. In order for T_OUT to function, PB1 must
be defined as an output line by setting PTBDIR bit 1 to 1.
Configured in this way, PB1 is capable of being a clock
output for T0, toggling the PB1 output pin on each T0 time-
out.
At end-of-count, the interrupt request line (IRQ0), clocks a
toggle flip-flop. The output of this flip-flop drives the T_OUT
line, PB1. In all cases, when T0 reaches its end-of-count,
T_OUT toggles to its opposite state (Figure 25). If, for exam-
ple, T0 is in Continuous Counting Mode, T_OUT exhibits a
50-percent duty cycle output. If the timer pair is selected
(T01) as a PWM, the duty cycle depends on the High and
Low reload values. At the end of each High time, PB1 tog-
gles Low. At the end of each Low time, PB1 toggles HI.
DS007500-Z8X0399
PRELIMINARY
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