Z8PE003 Datasheet, PDF(20/48 Page) Zilog, Inc. – FEATURE-ENHANCED Z8PLUS 1K ROM ONE-TIME PROGRAMMABLE (OTP) MICROCONTROLLER

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

Z8PE003 Datasheet, PDF (20/48 Pages) Zilog, Inc. – FEATURE-ENHANCED Z8PLUS 1K ROM ONE-TIME PROGRAMMABLE (OTP) MICROCONTROLLER

◁

Z8PE003

Z8Plus OTP Microcontroller

ZiLOG

IREQ SOFTWARE INTERRUPT GENERATION

IREQ can be used to generate software interrupts by spec-

ifying IREQ as the destination of any instruction referencing

the Z8Plus Standard Register File. These software inter-

rupts (SWI) are controlled in the same manner as hardware

generated requests. In other words, the IMASK controls the

enabling of each SWI.

To generate a SWI, the request bit in IREQ is set by the fol-

lowing statement:

OR IREQ,#NUMBER

The immediate data variable, NUMBER, has a 1 in the bit

position corresponding to the required level of SWI. For ex-

ample, an SWI must be issued when an IREQ5 occurs. Bit

5 of NUMBER must have a value of 1.

OR IREQ, #00100000B

If the interrupt system is globally enabled, IREQ5 is en-

abled, and there are no higher priority requests pending,

control is transferred to the service routine pointed to by the

IREQ5 vector.

Note: Software may modify the IREQ register at any time. Care

should be taken when using any instruction that modifies

the IREQ register while interrupt sources are active. The

software writeback always takes precedence over the

hardware. If a software writeback takes place on the

same cycle as an interrupt source tries to set an IREQ bit,

the new interrupt is lost.

Nesting of Vectored Interrupts

Nesting vectored interrupts allows higher priority requests

to interrupt a lower priority request. To initiate vectored in-

terrupt nesting, perform the following steps during the in-

terrupt service routine:

â¢ PUSH the old IMASK on the stack

â¢ Load IMASK with a new mask to disable lower prior-

ity interrupts

â¢ Execute an EI instruction

â¢ Proceed with interrupt processing

â¢ Execute a DI instruction after processing is complete

â¢ Restore the IMASK to its original value by POPing the

previous mask from the stack

â¢ Execute IRET

Depending on the application, some simplification of the

above procedure may be possible.

RESET Conditions

The IMASK and IREQ registers initialize to 00h on RESET.

PROGRAMMABLE OPTIONS

EPROM Protect. When selecting the DISABLE EPROM

PROTECT/ENABLE TESTMODE option, the user can read

the software code in the program memory. ZiLOGâs inter-

nal factory test mode, or any of the standard test mode meth-

ods, are useful for reading or verifying the code in the mi-

crocontroller when using an EPROM programmer. If the

user should select the ENABLE EPROM PROTECT/DIS-

ABLE TESTMODE option, it is not possible to read the code

using a tester, programmer, or any other standard method.

As a result, ZiLOG is unable to test the EPROM memory

at any time after customer delivery.

This option bit only affects the userâs ability to read the code

and has no effect on the operation of the part in an appli-

cation. ZiLOG tests the EPROM memory before customer

delivery whether or not the ENABLE EPROM PRO-

TECT/DISABLE TESTMODE option is selected; ZiLOG

provides a standard warranty for the part.

System Clock Source. When selecting the RC OSCILLA-

TOR ENABLE option, the oscillator circuit on the micro-

controller is configured to work with an external RC circuit.

When selecting the Crystal/Other Clock Source option, the

oscillator circuit is configured to work with an external

crystal, ceramic resonator, or LC oscillator.

PRELIMINARY

DS007500-Z8X0399

▷