Z8PE003 Datasheet, PDF (18/48 Pages) Zilog, Inc. – FEATURE-ENHANCED Z8PLUS 1K ROM ONE-TIME PROGRAMMABLE (OTP) MICROCONTROLLER

Z8PE003
Z8Plus OTP Microcontroller
INTERRUPT SOURCES
Table 10 presents the interrupt types, sources, and vectors
available in the Z8Plus. Other processors from the Z8Plus
family may define the interrupts differently.
ZiLOG
Table 10. Interrupt Types, Sources, and Vectors
Name
IREQ₀
IREQ₁
IREQ₂
IREQ₃
IREQ₄
IREQ₅
IREQ₆–IREQ₁₅
Sources
Timer0 Time-out
PB4 High-to-Low
Transition
Timer1 Time-out
PB2 High-to-Low
Transition
PB4 Low-to-High
Transition
Timer2 Time-out
Reserved
Vector Location
2,3
4,5
6,7
8,9
A,B
C,D
Comments
Fixed Priority
Internal
1 (Highest)
External (PB4), Edge 2
Triggered
Internal
3
External (PB2), Edge
Triggered
External (PB4), Edge
Triggered
Internal
4
5
6 (Lowest)
Reserved for future
expansion
External Interrupt Sources
External sources can be generated by a transition on the cor-
responding Port pin. The interrupt may detect a rising edge,
a falling edge, or both.
Notes: The interrupt sources and trigger conditions are device
dependent. See the device product specification to de-
termine available sources (internal and external), trig-
gering edge options, and exact programming details.
Although interrupts are edge triggered, minimum inter-
rupt request Low and High times must be observed for
proper operation. See the device product specification
for exact timing requirements on external interrupt re-
quests (T_WIL, T_WIH).
details. For more details on the interrupt sources, refer to
the chapters describing the timers, comparators, I/O ports,
and other peripherals.
Interrupt Mask Register (IMASK) Initialization
The IMASK register individually or globally enables or dis-
ables the interrupts (Table 11). When bits 0 through 5 are
set to 1, the corresponding interrupt requests are enabled.
Bit 7 is the master enable bit and must be set before any of
the individual interrupt requests can be recognized. Reset-
ting bit 7 disables all the interrupt requests. Bit 7 is set and
reset by the EI and DI instructions. It is automatically set to
0 during an interrupt service routine and set to 1 following
the execution of an Interrupt Return (IRET) instruction. The
IMASK registers are reset to 00h, disabling all interrupts.
Internal Interrupt Sources
Internal interrupt sources and trigger conditions are device
dependent. On-chip peripherals may set interrupt under var-
ious conditions. Some peripherals always set their corre-
sponding IREQ bit while others must be specifically con-
figured to do so.
See the device product specification to determine available
sources, triggering edge options, and exact programming
Notes: It is not good programming practice to directly assign a
value to the master enable bit. A value change should
always be accomplished by issuing the EI and DI in-
structions.
Care should be taken not to set or clear IMASK bits
while the master enable is set.
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PRELIMINARY
DS007500-Z8X0399