Z8PE003 Datasheet, PDF (19/48 Pages) Zilog, Inc. – FEATURE-ENHANCED Z8PLUS 1K ROM ONE-TIME PROGRAMMABLE (OTP) MICROCONTROLLER

ZiLOG
Table 11. Interrupt Mask Register—IMASK (FBh)
Bit
7 65 4 3 2 1 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
R = Read W = Write X = Indeterminate U = Undefined/
Undetermined
Bit
Position
7
R/W
6
5
4
3
2
1
0
Value
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
Description
Disables Interrupts
Enables Interrupts
Reserved, must be 0
Disables IRQ5
Enables IRQ5
Disables IRQ4
Enables IRQ4
Disables IRQ3
Enables IRQ3
Disables IRQ2
Enables IRQ2
Disables IRQ1
Enables IRQ1
Disables IRQ0
Enables IRQ0
Z8PE003
Z8Plus OTP Microcontroller
Interrupt Request (IREQ) Register Initialization
IREQ (Table 12) is a register that stores the interrupt re-
quests for both vectored and polled interrupts. When an in-
terrupt is issued, the corresponding bit position in the reg-
ister is set to 1. Bits 0 to 5 are assigned to interrupt requests
IREQ0 to IREQ5, respectively.
Whenever RESET is executed, the IREQ resistor is set to
00h.
Table 12. Interrupt Request Register–IREQ (FAh)
Bit
R/W
Reset
7 65 4 3 2 1 0
R/W R/W R/W R/W R/W R/W R/W R/W
0 00 0 0 0 0 0
R = Read W = Write X = Indeterminate U = Undefined/
Undetermined
Bit
Position
7
R/W
R/W
Value Description
0 Reserved, must be 0
6
R/W
0 Reserved, must be 0
5
R/W
0 IRQ5 reset
1 IRQ5 set
4
R/W
0 IRQ4 reset
1 IRQ4 set
3
R/W
0 IRQ3 reset
1 IRQ3 set
2
R/W
0 IRQ2 reset
1 IRQ2 set
1
R/W
0 IRQ1 reset
1 IRQ1 set
0
R/W
0 IRQ0 reset
1 IRQ0 set
DS007500-Z8X0399
PRELIMINARY
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