Z87010 Datasheet, PDF (21/22 Pages) Zilog, Inc. – Audio Encoder/Decoders

Zilog
Z87010/Z87L10
Audio Encoder/Decoders
OPERATION
Disabling Peripherals
Disabling a properly (CODEC Interface, Counter) provides
a general-purpose use of the EXT address pertaining to
the specific peripheral. If the peripheral is not disabled, the
written to while the serial CODEC transfer is taking place.
This is achieved by only writing to EXT5 after the CODEC
interrupt. This also transfers the CODEC value to EXT5-1
which can be read in software.
2
EXT control signals and EXT data are still provided but _{The correct succession of operations is thus}
transfer of data on the EXT pins is not available (since in-
ternal transfers are being processes on the internal bus). _{1. Wait for Interrupt}
Care must be taken to ensure that control of the EXT bus _{2. Write to EXT5}
does not provide bus conflicts.
3. Read from EXT5
Accessing the CODEC Interface Registers
EXT5, EXT6 AND EXT7 host double buffered registers.
External serial CODEC data is transferred from pin RxD to
the Z87010 CODEC interface registers EXT5-2. At the
same time, the data present in EXT5-2 is serially trans-
ferred to the external CODEC through pin TxD.
Writing a new data word to EXT5 loads that data word to
EXT5-2 and transfers the current contents of EXT5-2 to
EXT5-1. Reading data from EXT5 reads the contents of
EXT5-1. Core must be taken to ensure that EXT5 is not
The same discussion applies for EXT6.
A similar hardware architecture is used for EXT7. Writing
to EXT7 loads the register EXT7-2 and transfers the previ-
ous contents of EXT7-2 to EXT7-1. Reading from EXT7 re-
turns the contents of EXT7-1.
In order to load both registers, two successive load opera-
tions to EXT7 are required: first with the contents of EXT7-
1 then with the contents of EXT7-2. (See Figure 16).
Internal 16-Bit Bus
16
16
EXT7-1
EXT7-2
EXT7-1 CODEC Timer Register
EXT7-2 Wait-State Register
Figure 16. EXT7 Register Configuration
DS96WRL0601
PRELIMINARY
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