Z87010 Datasheet, PDF (16/22 Pages) Zilog, Inc. – Audio Encoder/Decoders

Z87010/Z87L10
Audio Encoder/Decoders
Zilog
CODEC INTERFACE
The CODEC interface provides direct-connect capabilities
for standard 8-bit PCM CODECs with hardware µ-law
compression. Internal registers EXT5, EXT6 and EXT7 are
used to program the CODEC mode. One serial clock and
two frame sync control signals are provided, allowing for
two bidirectional data channels.
Note: µ-law expansion must be done in software.
16
EXT5-1
CLKIN
16
Data Bus
16
EXT6-1
CLKIN
16
16
µ-Law
Compression
EXT7-1
16
16
EXT5-2
CLKIN
EXT6-2
CLKIN
CLKIN
TXD
CONTROL
LOGIC
RXD
Figure 9. CODEC Interface Block Diagram
EXT7-2
CODEC Interface Hardware
The Hardware for the CODEC Interface uses six 16-bit
registers, µ-law compression logic and general-purpose
logic to control transfers to the appropriate register.
CODEC Interface Control Signals
SCLK (Serial Clock)
The Serial Clock provides a clock signal for operating the
external CODEC. A 4-bit prescaler is used to determine
the frequency of the output signal.
SCLK = (0.5* CLK)/PS where: CLK = System Clock
PS = 4-bit Prescaler*
Note: An internal divide-by-two is performed before the
clock signal is passed to the Serial Clock prescaler.
* The Prescaler is an up-counter.
2-16
PRELIMINARY
DS96WRL0601