Z87010 Datasheet, PDF (18/22 Pages) Zilog, Inc. – Audio Encoder/Decoders

Z87010/Z87L10
Audio Encoder/Decoders
CODEC INTERFACE (Continued)
The CODEC interface timing is independent of the proces-
sor clock when external mode is chosen. This feature pro-
vides the capability for an external device to control the
transfer of data to the Z87010. The Frame Sync signal en-
velopes the transmitted data (Figure 10), therefore care
must be taken to ensure proper sync signal timing. In the
cordless phone system, the SCLK is externally provided
by the Z87000 controller, while FSYNC is internally gener-
ated.
The Transmit and Receive lines are used for transfer of se-
rial data to or from the CODEC interface. The CODEC in-
terface performs both data transmit and receive simulta-
neously.
Zilog
The FSYNC Signals (FS0, FS1) when programmed for in-
ternal mode, are generated by 9-bit counter with SCLK as
input clock. Together with the SCLK prescaler, this counter
forms a 13-bit counter clocked by the system clock divided
by two. The output of this counter can be used to clock the
general-purpose 13-bit counter/timer, to form a 26-bit
counter.
CODEC Control Registers
The CODEC interface is accessed through addresses
EXT5, EXT6 and EXT7. The data accesses are double-
buffered registers: two registers (EXT5-1 and EXT5-2) are
mapped on address EXT5 and similarly EXT6-1 and
EXT6-2 registers are mapped on address EXT6.
EXT5-1
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
EXT5-2
Data Bits 15-0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Data Bits 15-0
Figure 11. CODEC Interface Data Registers (Channel 0)
EXT6-1
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
EXT6-2
Data Bits 15-0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Data Bits 15-0
Figure 12. CODEC Interface Data Registers (Channel 1)
2-18
PRELIMINARY
DS96WRL0601