Z87010 Datasheet, PDF(19/22 Page) Zilog, Inc.

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Z87010 Datasheet, PDF (19/22 Pages) Zilog, Inc. – Audio Encoder/Decoders

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Zilog

Z87010/Z87L10

Audio Encoder/Decoders

EXT7-1

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Note: The timer is an up-counter.

Example: EXT7-1 = #%x00D

EXT7-1 = #%x80F

EXT7-1 = #%xFFx

EXT7-1 = #%x000

OSC = 12.288 MHz, SCLK = 2.048 MHz, FSYNC = 8 kHz

OSC = 12.288 MHz, SCLK = 6.144 MHz, FSYNC = 48 kHz

No interrupt

Max interrupt period (667 Âµs for OSC = 12.288 MHz)

SCLK Prescaler (up-counter)

SCLK/FSYNC Ratio Prescaler (up-counter)

CODEC Mode

01 Reserved

10 Reserved

11 Reserved

FSYNC

0 External Source*

1 Internal Source

CODEC 0 Disable/Enable

0 = Disable*

1 = Enable

* Default

Figure 13. CODEC Interface Control Register

EXT7-2

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Wait State EXT0

Wait State EXT1

Wait State EXT2

Wait State EXT3

Wait State EXT4

Wait State EXT5

nws - no wait states

ws - one wait states

00 no wait states (nws)

01 read (nws), write (ws)

10 read (ws), write (nws)

11 read (ws), write (ws)

Wait State EXT6

SCLK

0 External Source*

1 Internal Source

CODEC 1 Disable/Enable

0 = Disable*

1 = Enable

*Default

Figure 14. Wait/State/CODEC Interface Control Register

DS96WRL0601

PRELIMINARY

2-19

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